三维可重构阵列自主容错方法研究

发布时间：2018-06-10 01:35

本文选题：三维可重构阵列 + 自主容错　；参考：《南京航空航天大学》2013年硕士论文

【摘要】：随着集成电路技术的飞速发展，数字电子系统的集成度大幅提高，在生命周期内发生故障的概率也随之增加。可重构硬件具有功能灵活、开发周期短等优点，，已广泛应用于航空航天等领域的关键电子系统中，由于工作环境恶劣且人工难以维护，对可重构硬件的可靠性要求更高。因此，以提高可靠性为目标的可重构硬件容错设计具有重要意义。可重构硬件的自主容错是指在不需要外部控制器进行控制的情况下，实现故障自主修复。目前二维可重构硬件的自主容错方法中，重布线机制不易实现，特别是在一些大规模系统中，布线拥塞和延迟现象严重，导致容错时间开销大，容错能力不高。三维阵列结构可显著减少布线长度，提高布线过程布通率和布线机制灵活性，给可重构硬件的容错方法设计提供了新思路。本文利用三维阵列结构在布线灵活性方面的优势，对三维可重构阵列的自主容错方法进行研究，论文的主要研究工作如下：（1）设计了一种三维结构的可重构阵列，可有效改善二维可重构硬件重布线机制不灵活，容错控制复杂度随阵列规模增大而增加，难以大规模实现等问题，并且在此结构上对功能细胞和三维开关块进行了容错设计，使可重构阵列具有自主容错能力。三维开关块用于实现功能细胞在六个方向上的信息传递，提高了布线机制灵活性的同时，还具有在线自测试与自修复能力；功能细胞内部设有容错控制模块，可实现细胞的在线自主容错，减少容错控制复杂度。（2）对可重构硬件的自主容错方法进行了研究，采用在线分布式输入测试向量的方法，能够对故障进行精确定位，测试速度快且测试机制实现简单；容错过程中，采用分层修复方法，根据诊断结果执行相应修复机制，对细胞内底层冗余资源和可重构阵列空闲互连资源进行合理利用，充分提高资源利用率和容错速率。（3）本文最后以四位并行乘法器和四位加法/减法器为例，在三维可重构阵列上实现功能映射，对其进行仿真和下板测试，验证了可重构阵列的逻辑功能与自主容错能力，并且在容错能力、硬件资源开销和容错时间开销三方面与其他典型可重构硬件容错技术进行了分析对比，说明本文提出的三维可重构阵列自主容错方法具有容错能力高，硬件资源开销小和容错速度快等优势。
[Abstract]:With the rapid development of integrated circuit technology, the integration of digital electronic system has been greatly improved, and the probability of failure in the life cycle has also increased. Reconfigurable hardware has the advantages of flexible function and short development cycle. It has been widely used in the key electronic systems in aerospace and other fields. Because of the harsh working environment and difficult to maintain, the reliability of reconfigurable hardware is higher than that of reconfigurable hardware. Therefore, it is of great significance to improve the reliability of reconfigurable hardware fault-tolerant design. The autonomous fault tolerance of reconfigurable hardware refers to the implementation of autonomous fault recovery without the need of external controller control. At present, the rerouting mechanism is not easy to implement in two-dimensional reconfigurable hardware, especially in some large-scale systems, the routing congestion and delay are serious, resulting in a large amount of fault-tolerant time overhead and low fault-tolerant ability. Three-dimensional array structure can significantly reduce routing length, improve routing process routing rate and routing mechanism flexibility, and provide a new idea for fault tolerant design of reconfigurable hardware. This paper makes use of the advantages of three-dimensional array structure in routing flexibility. The main work of this paper is as follows: 1) A reconfigurable array with 3D structure is designed, which can effectively improve the rerouting mechanism of two-dimensional reconfigurable hardware. The complexity of fault-tolerant control increases with the increase of array size, which is difficult to implement on a large scale. In this structure, fault-tolerant design for functional cells and 3D switching blocks is carried out to make the reconfigurable array have autonomous fault-tolerant capability. Three-dimensional switch block is used to realize information transmission in six directions of functional cells, which improves the flexibility of routing mechanism, and also has the ability of on-line self-testing and self-repairing, and has fault-tolerant control module inside functional cells. It can realize the on-line autonomous fault-tolerant of cells and reduce the complexity of fault-tolerant control. (X2) the autonomous fault-tolerant method of reconfigurable hardware is studied. The method of on-line distributed input test vector can accurately locate the fault. In the process of fault tolerance, the hierarchical repair method is used to carry out the corresponding repair mechanism according to the diagnosis results, and the redundant resources in the bottom layer of the cell and the idle interconnection resources of the reconfigurable array are reasonably utilized. Finally, taking four bit parallel multiplier and four bit addition / subtraction as examples, we implement functional mapping on 3D reconfigurable array, simulate it and test it on the bottom board. The logic function and autonomous fault-tolerant ability of reconfigurable array are verified and compared with other typical reconfigurable hardware fault-tolerant techniques in three aspects: fault-tolerant capability, hardware resource overhead and fault-tolerant time cost. It is shown that the autonomous fault-tolerant method of 3D reconfigurable array presented in this paper has the advantages of high fault-tolerant capability, low cost of hardware resources and fast fault-tolerant speed.
【学位授予单位】：南京航空航天大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP302.8

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