多核处理器初始化及高速IO接口设计

发布时间：2018-06-16 20:10

本文选题：MPSoC + 通讯架构　；参考：《南京大学》2012年硕士论文

【摘要】：片上多核系统MPSoC(Multiprocessor System-on-Chip)能够充分利用多处理器的数据并行处理能力以及SoC的高集成度,针对目标应用的多样性进行定制化的设计,从而使系统的硬件结构更好地满足目标应用的需求,能够最大限度地提升系统的整体性能。众多MPSoC通讯架构地提出,为满足复杂应用的大规模运算和实时性需求提供了可行的解决办法,正逐渐演变为多处理器系统和下一代集成电路设计的主流趋势。本文描述和分析了MPSoC基本通讯架构模型,提出了一种多核初始化方案。该方案将Flash存储器连接到片上通讯网络的通讯节点上作为初始化数据源,采用发送网络数据包的方式逐一对多核系统中的多个处理器核进行初始化,同时采用引导程序与用户主程序分开设计的方法,使得引导程序的设计具有较好的独立性和可移植性。设计中的Flash Wrapper模块完成从Flash接口协议到PCC协议的转化,依靠状态机来实现链路的建立和数据的传输,同时给予实验,实现每个簇中核的初始化。此外对Rocket10进行了介绍和分析,并简述了Aurora协议以及8b/10b编解码,在此基础上设计了基于多核芯片数据传输的Rocket10Wrapper,实现数据的高速传输。基于Xilinx的FPGA开发平台,我们对整个系统进行了FPGA原型实现,分步验证模块设计与数据传输。
[Abstract]:Multi-core system MPSoC / Multiprocessor System-on-Chip (MPSoC) can make full use of the multi-processor data parallel processing ability and the high integration of SoC, and can customize the diversity of target applications. Thus, the hardware structure of the system can better meet the requirements of the target application, and the overall performance of the system can be greatly improved. Many MPSoC communication architectures are proposed, which provide a feasible solution to meet the needs of large-scale computing and real-time of complex applications, and are gradually becoming the mainstream trend of multi-processor systems and next-generation integrated circuit design. This paper describes and analyzes the MPSoC basic communication architecture model and proposes a multi-core initialization scheme. In this scheme, Flash memory is connected to the communication node of the communication network on chip as the initialization data source, and the multi-processor cores in the multi-core system are initialized by sending the network data packets. At the same time, the bootstrap program is designed separately from the user's main program, which makes the bootstrap design more independent and portable. The Flash wrapper module is designed to realize the conversion from Flash interface protocol to PCC protocol. The state machine is used to realize the link establishment and data transmission. At the same time, the experiment is carried out to initialize the core in each cluster. In addition, Rocket10 is introduced and analyzed, and the Aurora protocol and 8b/10b codec are briefly described. On this basis, Rocket10Wrapper-based multi-core chip data transmission is designed to realize high-speed data transmission. Based on the FPGA development platform of Xilinx, we implemented the whole system with FPGA prototype, step by step verification module design and data transmission.
【学位授予单位】：南京大学
【学位级别】：硕士
【学位授予年份】：2012
【分类号】：TP332;TN47

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