异构五核XDSP调度机制的设计与实现
发布时间：2018-07-15 13:52
【摘要】：高速发展的处理器技术已经发生了革命性的变化，多核处理器逐渐代替单核处理器成为处理器技术主流。作为通用微处理器的一个分支，数字信号处理器即DSP也跨进了以多核，尤其是异构多核DSP为主导的高速发展时代。 嵌入式异构多核DSP处理器是软硬件协同设计的面向应用的专用微处理器。从应用角度而言，提升用户体验的努力不仅仅体现在升级操作系统，，更在于开发更合适的硬件机制。任务调度是操作系统和硬件系统需要共同关注的环节。异构多核处理器体系结构的出现为任务调度问题带来了新的变化，如何设计能够有效实现任务调度的硬件机制来支撑任务调度算法实现，使异构多核处理器系统能够充分发挥性能已经成为亟待解决的问题。在嵌入式异构多核DSP处理器操作系统中，多核任务的调度根据多核任务调度算法实现。而多核任务调度的算法运作实际上是通过调用调度机制的驱动程序，从而驱动底层硬件运作的过程。在整个任务调度机制中，底层的硬件是基础，驱动程序是支撑。 本文以国防科技大学计算机学院研制的高性能异构五核XDSP设计工程为背景，为XDSP设计了能够有效支持多核任务调度的底层硬件机制和配套的驱动程序，是XDSP多核系统能够顺利运行并发挥其性能的保障。本文主要完成了以下工作： 基于XDSP的体系结构特点和丰富的片上资源，为XDSP设计了硬件调度机制，实现了MCU子系统和DSP子系统间的数据通信和MCU对DSP子系统的控制； 配合XDSP多核调度的硬件机制，设计了配套的驱动程序，包括多种BOOT模式下的BOOT程序，实施调度和任务同步的交叉中断处理程序等，为调度机制的运行提供了驱动支撑； 分别在模块级和系统级对调度机制进行了模拟功能验证，验证中组合使用了覆盖率驱动的验证方法，基于断言的验证方法和软硬件协同仿真等验证方法； 实现了XDSP的FPGA原型设计，对调度机制进行了较全面的系统级仿真验证，并据此实现了JPEG解码程序在XDSP上的任务分派和调度。
[Abstract]:The rapid development of processor technology has undergone a revolutionary change, multi-core processors have gradually replaced single-core processors into the mainstream of processor technology. As a branch of universal microprocessor, DSP (Digital signal processor) has also stepped into the era of high speed development with multi-core, especially heterogeneous multi-core DSP. Embedded heterogeneous multi-core DSP processor is an application-oriented microprocessor which is codesigned by hardware and software. From an application point of view, efforts to enhance the user experience are not only reflected in upgrading the operating system, but also in developing more appropriate hardware mechanisms. Task scheduling is a link that the operating system and hardware system need to pay attention to. The emergence of heterogeneous multi-core processor architecture has brought new changes to the task scheduling problem. How to design a hardware mechanism that can effectively implement task scheduling to support the implementation of task scheduling algorithm. It has become an urgent problem to make heterogeneous multi-core processor system give full play to its performance. In embedded heterogeneous multi-core DSP processor operating system, the scheduling of multi-core tasks is based on multi-core task scheduling algorithm. The algorithm operation of multi-core task scheduling is actually the process of driving the underlying hardware operation by calling the driver of the scheduling mechanism. In the whole task scheduling mechanism, the underlying hardware is the foundation and the driver is the support. Based on the design engineering of high performance heterogeneous five-core XDSP developed by computer School of National University of National Defense Science and Technology, this paper designs the underlying hardware mechanism and supporting driver for XDSP, which can effectively support multi-core task scheduling. It is the guarantee that XDSP multi-core system can run smoothly and give full play to its performance. The main work of this paper is as follows: based on the architecture characteristics of XDSP and abundant on-chip resources, the hardware scheduling mechanism is designed for XDSP, the data communication between MCU subsystem and DSP subsystem is realized and MCU controls DSP subsystem; With the hardware mechanism of XDSP multi-core scheduling, a complete set of drivers is designed, including the boot program in various boot modes, the cross-interrupt processing program for scheduling and task synchronization, and so on. It provides driving support for the operation of the scheduling mechanism, and simulates the scheduling mechanism at the module level and the system level, and combines the coverage driven verification method in the verification. The verification methods based on assertion and hardware / software co-simulation are implemented, the FPGA prototype design of XDSP is implemented, and the scheduling mechanism is verified by system-level simulation. Based on this, the task assignment and scheduling of JPEG decoding program on XDSP are realized.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332
本文编号：2124290
[Abstract]:The rapid development of processor technology has undergone a revolutionary change, multi-core processors have gradually replaced single-core processors into the mainstream of processor technology. As a branch of universal microprocessor, DSP (Digital signal processor) has also stepped into the era of high speed development with multi-core, especially heterogeneous multi-core DSP. Embedded heterogeneous multi-core DSP processor is an application-oriented microprocessor which is codesigned by hardware and software. From an application point of view, efforts to enhance the user experience are not only reflected in upgrading the operating system, but also in developing more appropriate hardware mechanisms. Task scheduling is a link that the operating system and hardware system need to pay attention to. The emergence of heterogeneous multi-core processor architecture has brought new changes to the task scheduling problem. How to design a hardware mechanism that can effectively implement task scheduling to support the implementation of task scheduling algorithm. It has become an urgent problem to make heterogeneous multi-core processor system give full play to its performance. In embedded heterogeneous multi-core DSP processor operating system, the scheduling of multi-core tasks is based on multi-core task scheduling algorithm. The algorithm operation of multi-core task scheduling is actually the process of driving the underlying hardware operation by calling the driver of the scheduling mechanism. In the whole task scheduling mechanism, the underlying hardware is the foundation and the driver is the support. Based on the design engineering of high performance heterogeneous five-core XDSP developed by computer School of National University of National Defense Science and Technology, this paper designs the underlying hardware mechanism and supporting driver for XDSP, which can effectively support multi-core task scheduling. It is the guarantee that XDSP multi-core system can run smoothly and give full play to its performance. The main work of this paper is as follows: based on the architecture characteristics of XDSP and abundant on-chip resources, the hardware scheduling mechanism is designed for XDSP, the data communication between MCU subsystem and DSP subsystem is realized and MCU controls DSP subsystem; With the hardware mechanism of XDSP multi-core scheduling, a complete set of drivers is designed, including the boot program in various boot modes, the cross-interrupt processing program for scheduling and task synchronization, and so on. It provides driving support for the operation of the scheduling mechanism, and simulates the scheduling mechanism at the module level and the system level, and combines the coverage driven verification method in the verification. The verification methods based on assertion and hardware / software co-simulation are implemented, the FPGA prototype design of XDSP is implemented, and the scheduling mechanism is verified by system-level simulation. Based on this, the task assignment and scheduling of JPEG decoding program on XDSP are realized.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2013
【分类号】：TP332
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相关期刊论文 前2条
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2 刘必慰;陈书明;汪东;;先进微处理器体系结构及其发展趋势[J];计算机应用研究;2007年03期
本文编号：2124290
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