基于FPGA和USB2.0总线的多路数据采集系统开发

发布时间：2018-06-02 05:21

本文选题：塔式起重机 + 安全预警系统　；参考：《长安大学》2011年硕士论文

【摘要】：本文根据塔式起重机安全预警系统研究内容及总体设计要求，研究并设计了一种基于FPGA和USB2.0总线技术的多路数据采集系统，，用来采集、传输和分析基于超声波测障的回波信号。本系统由主机和采集板组成。主机主要实现多通道采集数据的分离、分析和存储功能；采集板以FPGA为系统的控制核心，实现多路数据的并行采集功能，主机和采集板之间通过USB2.0数据总线进行通信，可以实现多路实时超声回波信号的并行采集和存储。在硬件方面，本文设计了FPGA采集控制电路、ADC LTC1609前端数据采集电路、SDRAM数据乒乓缓存电路以及FX2LP USB接口电路等。在USB2.0数据总线方面，本文以USB2.0协议为基础，分析了FX2LP的固件工作原理和编写框架，设计了基于FX2LP接口芯片并且符合USB2.0高速协议的通讯接口。在FPGA控制模块方面，本文设计了多路数据并行采集模块、数据乒乓缓冲模块、USB数据传输模块、主机命令解码模块。其中多路数据并行采集模块对多路滤波放大后的输入信号进行并行采集，采样率可调；数据乒乓缓冲模块负责对采样得到的数据进行缓存；USB数据传输模块负责将缓存后的数据按照FX2LP的工作时序送到FX2LP的数据总线上；主机命令解码模块负责对主机发送的控制命令进行解码，控制数据采集硬件。本文使用ModelSim仿真工具对各个模块的功能做了时序仿真，并在硬件上对数据采集和控制功能进行了测试，测试结果表明本数据采集系统符合项目指标。
[Abstract]:According to the research content and overall design requirement of tower crane safety warning system, this paper studies and designs a multi-channel data acquisition system based on FPGA and USB2.0 bus technology, which is used to collect, transmit and analyze echo signals based on ultrasonic barrier measurement. This system is composed of mainframe and acquisition board. The main function of the host computer is to separate, analyze and store the multi-channel data, and the acquisition board takes FPGA as the control core of the system, realizes the multi-channel data parallel acquisition function, and communicates between the host and the acquisition board through the USB2.0 data bus. The parallel acquisition and storage of multi-channel real-time ultrasonic echo signal can be realized. In the aspect of hardware, this paper designs FPGA acquisition control circuit and LTC1609 front-end data acquisition circuit, SDRAM data ping-pong buffer circuit and FX2LP USB interface circuit. In the aspect of USB2.0 data bus, based on the USB2.0 protocol, this paper analyzes the working principle and programming framework of the firmware of FX2LP, and designs the communication interface based on FX2LP interface chip and accord with the high speed protocol of USB2.0. In the aspect of FPGA control module, this paper designs a multi-channel parallel data acquisition module, a data ping-pong buffer module, a FPGA data transmission module, and a host command decoding module. The multi-channel parallel data acquisition module collects the input signal after multi-channel filtering and amplifying, and the sampling rate can be adjusted. The data ping-pong buffer module is responsible for caching the sampled data. The USB data transfer module is responsible for sending the cached data to the FX2LP data bus according to the working sequence of FX2LP. The host command decoding module is responsible for decoding the control command sent by the host computer and controlling the data acquisition hardware. In this paper, the function of each module is simulated with ModelSim simulation tool, and the data acquisition and control functions are tested in hardware. The test results show that the data acquisition system accords with the project index.
【学位授予单位】：长安大学
【学位级别】：硕士
【学位授予年份】：2011
【分类号】：TP274.2;TH213.3

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