基于FPGA的高效LDPC译码器的研究

发布时间：2018-01-04 17:27

本文关键词：基于FPGA的高效LDPC译码器的研究　出处：《北京交通大学》2014年硕士论文　论文类型：学位论文

【摘要】：摘要：低密度奇偶校验(LDPC)码是一种近Shannon限高效线性分组码,已为许多通信标准采纳。现代高速通信对译码器速率的要求,使得LDPC码的硬件译码器设计与实现成为LDPC码研究领域的热点。FPGA具有并行性和高速运行的特点,成为LDPC译码器的不二之选,本文的工作亦基于FPGA平台实现。在分析比较了LDPC码的几种软判决译码算法,综合考虑了算法的复杂度和译码性能后,选择了性能优异且复杂度较低的最小和算法作为译码器的算法基础。以此为契机,针对目前LDPC码硬件译码器结构不够灵活、片上资源消耗偏大的问题,提出了基于最小和算法的两种高效LDPC译码器,并在Xilinx公司的FPGA平台上验证。一种是适用于所有LDPC码的可配置的译码器,它将所有码都当做随机码进行处理,对译码过程中信息存储方式的优化和流水线的处理方式,在保证吞吐量的前提下,使译码器最大限度地减少了片上资源的消耗。分别选择了准循环LDPC码和随机LDPC码进行验证,与传统的部分译码器相比,该译码器使用的片上RAM资源比部分译码器降低一半以上,同时吞吐量几乎保持不变。另一种则充分利用了准循环LDPC码的特点,能够并行更新校验节点和变量节点的高吞吐量译码器。在校验节点更新结束后,对信息进行存储的同时,通过地址映射对变量节点进行处理,从而消除了变量节点和校验节点更新之间的等待时间,使得译码器的吞吐量得到提升。选择了IEEE802.11ad标准中1/2码率的LDPC码字在BPSK调制模式下进行仿真,当主频为100MHz时,得到：200Mbps的吞吐量。与传统的部分译码器相比,吞吐量提高了将近1/3。为了对译码器的译码性能进行验证,在Xilinx Spartan-6FPGA平台上设计实现了LDPC码仿真系统的全部子模块,包括编译码模块,高斯噪声发生器,信道模拟模块。仿真结果表明,硬件译码器的性能与Matlab得到的结果一致。
[Abstract]:Abstract: low density parity check (LDPC) code is a linear block code near Shannon limit performance, has been applied in many communication standards. The requirements of modern high speed communication rate of the decoder, which makes the design and implementation of hardware decoder of LDPC code LDPC code.FPGA has become a hot research field is parallel and high speed characteristics, become the LDPC decoder's choice, the work of this paper is based on the FPGA platform. In the analysis and comparison of several soft decision LDPC decoding algorithm, considering the complexity of the algorithm and the decoding performance, selection of excellent performance and low complexity minimum sum algorithm as the algorithm based decoder. This opportunity in view of the current LDPC hardware decoder structure is not flexible enough, on-chip resource consumption is too large for the problem, propose two efficient LDPC decoder and minimum algorithm based on FPGA, and in Xilinx's flat Verifying on the platform.
A LDPC code is applicable to all configurable decoder, it will be all the code as a random code for processing, processing and optimization of assembly line of information stored in the decoding process, on the premise of ensuring the throughput, the decoder minimizes the on-chip resource consumption. Choose the quasi cyclic LDPC codes and random LDPC code validation, compared with traditional decoder, the decoder uses on-chip RAM resources to reduce more than half part of the decoder, and the throughput remains almost unchanged.
The other is to make full use of the characteristics of quasi cyclic LDPC codes, a high throughput decoder to update the check nodes and variable nodes in parallel. Check node update after the storage of information at the same time, based on the variable node address mapping process, thus eliminating the waiting time between updating the variable nodes and check nodes. The throughput of the decoder are improved. Choose the LDPC code in IEEE802.11ad standard 1/2 rate is simulated in the BPSK modulation mode, when the frequency is 100MHz, 200Mbps throughput. Compared with the traditional part of the decoder, the throughput is increased by nearly 1/3.
In order to verify the decoding performance of the decoder, the design and implementation of all LDPC code simulation module in Xilinx Spartan-6FPGA platform, including the encoding and decoding module, Gauss noise generator, channel simulation module. The simulation results show that the performance of Matlab hardware decoder obtains the same results.

【学位授予单位】：北京交通大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN911.22

【共引文献】