电源噪声引起CMOS锁相环的周期抖动研究

发布时间：2018-01-05 23:21

本文关键词：电源噪声引起CMOS锁相环的周期抖动研究　出处：《西安电子科技大学》2014年硕士论文　论文类型：学位论文

【摘要】：抖动的大小作为衡量信号完整性的一个技术指标,而电源噪声是时序抖动的最重要的成因。在电源完整性方面,通过提供一个稳定的电源分配网络(PDN)来最大限度的减小电源噪声,以此达到减小时序抖动的目的。但是,在高速的系统中封装呈现出很大电感性,因此我们设计PDN时不可能将OI/接口产生的电源噪声忽略不计。锁相环作为serdes电路,频率合成器中的时序最敏感模块,所以我们很有必要对锁相环系统中的电源噪声和抖动的关系进行深入研究。本文首先介绍了电源噪声对电子系统的影响以及对电源分配网络模型进行了讲解以减小电源噪声;又对抖动进行了系统的阐述,主要介绍了相位抖动,周期抖动以及周期间抖动之间的关系;阐述了锁相环电路的发展及结构,并对传统的用于教学的锁相环电路结构的每个模块进行了改进,用Hspice建立此锁相环的模型,并且通过眼图对抖动的大小进行度量,使在无电源噪声的情况下,锁相环的自身的抖动足够低,以使增加此锁相环的可靠性及可用性。通过给此改进的锁相环电路加不同频率的电源噪声(电源噪声的幅值不变),研究不同电源噪声频率下抖动和电源噪声的关系。目前已经有一些关于抖动的建模以及环形振荡器的相位噪声研究。抖动的模型得到的是环形振荡器的抖动和相位噪声的表达式,但是,环形振荡器的分析可能不适合于锁相环,因为锁相环的影响因素多于环形振荡器。还有一种基于宏模型的锁相环的快速准确的分析,尽管它可以减少分析噪声影响时仿真的复杂性,但是当锁相环的结构被改变时宏模型不得不被重新建立。另外一种方法是假设抖动响应是电源噪声的线性函数的前期下,抖动的灵敏度是一种有效的手段用于表征电源噪声引起的抖动,但是抖动灵敏度瞬态分析是非常耗时的,为了节省仿真时间,虽然提出了能快速得到抖动的灵敏度曲线的方法。但是,不衔接的问题阻碍了它的应用。相位抖动,周期抖动与周期间抖动是对抖动的不同定义,我们研究发现周期抖动和电源噪声存在更好的线性关系。基于这种线性关系,求出了周期抖动和混合频率下的电源噪声的线性的关系表达式,利用这个表达式,可以预测电源噪声引起的锁相环的周期抖动。利用所求的表达式计算得到的抖动值和利用hspice仿真测量的抖动值进行对比,验证表达式的正确性及可用性。最后,文章还讨论了压控振荡器控制电压对锁相环整个系统的抖动的影响。
[Abstract]:The size of the jitter as a technical measure of signal integrity, and power supply noise is the important cause of timing jitter. In power integrity, by providing a stable power distribution network (PDN) to reduce the noise of power, in order to achieve the purpose of decreasing order jitter. However, in high speed system package shows great inductive power supply noise, so we design PDN OI/ interface will not be produced negligible. The PLL frequency synthesizer circuit as SerDes timing, the most sensitive module, so it is necessary for us to study the relationship of PLL system in power supply noise and jitter. This paper first introduces the influence of noise on the power electronic system and the power distribution network model are introduced to reduce the noise of power; and makes a systematic exposition of the main jitter. Introduces the relationship between phase jitter, cycle jitter and cycle cycle jitter; expounds the development and structure of PLL circuit for each module and the traditional teaching of the PLL circuit structure was improved, the establishment of PLL model with Hspice, measure and through the eye diagram of jitter size, make in the absence of power supply noise, PLL's jitter is low enough, in order to increase the reliability and usability of the PLL. The power supply noise by phase-locked loop circuit to improve the different frequency (amplitude and power supply noise does not change), study the different power supply noise frequency jitter and noise power relationship at present there have been some modeling about jitter and ring oscillator phase noise research. Jitter model is derived, jitter and phase noise of ring oscillator but ring oscillator The analysis may not be suitable for phase locked loop PLL, because of the impact factor than the ring oscillator. There is also a macro model based on phase locked loop of fast and accurate analysis, although it can reduce the complexity of the simulation analysis of the influence of noise, but when the PLL structure is changed when the macro model had to be re established. Another method is that the response is a linear function of the jitter of the power supply noise, jitter sensitivity is an effective means for the characterization of the power supply noise caused by jitter, but the jitter sensitivity of the transient analysis is very time-consuming, in order to save simulation time, although the proposed method can quickly obtain the sensitivity curve of jitter. However, no connection the problems that hinder its application. The phase jitter, cycle jitter and jitter during the week is different definitions of jitter, we found that the cycle jitter and noise power There is a linear relationship between the sound better. This linear relationship based on the calculated formulas of the linear power supply noise jitter and mixed frequency of the use of this expression can predict the periodic jitter phase locked loop. The power supply noise caused by HSPICE simulation and the measured jitter value comparison value calculated by the formula for the jitter, correctness and usability validation expression. Finally, the influence of the VCO control voltage of PLL jitter of the system is discussed.

【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN911.8

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