用于视频监控平台的JPEG2000压缩系统的FPGA实现

发布时间：2018-01-08 02:01

本文关键词：用于视频监控平台的JPEG2000压缩系统的FPGA实现　出处：《华南理工大学》2014年硕士论文　论文类型：学位论文

【摘要】：在高性能视频监控系统中，考虑到传输带宽、外部存储空间的限制以及特定场合图像的无损获取，要求采集端对图像数据能够无损压缩传输。本文基于某公司的视频监控处理平台，采用FPGA实现了JPEG2000图像压缩系统。主要工作如下： 1、在实现JPEG2000压缩系统的FPGA结构上，采用模块化的设计方式把整个压缩系统分为预处理模块、分量变换模块、小波变换模块、系数量化模块、Tier1编码器和Tier2编码器模块。 2、在小波变换模块:根据实现无损压缩的需求，，采用提升5/3离散小波，并且根据小波变换中提升系数的特点，采用映射结构替代通常的乘法运算，减少了关键路径延时，提升了变换速度；根据提升步骤的分裂、预测和更新特点，利用三级流水线实现一维小波变换，优化了硬件资源和速度。 3、在编码器模块：Tier1模块包含了位平面编码和算术编码。位平面编码器的设计采用通道并行方案；在算术编码器的实现方式上，采用自适应二进制算术编码和五级流水线方式，提升了编码器的效率。在Tier2编码器模块，根据JPEG2000编码规则，对Tier1编码器输出的压缩数据进行码流组织；根据处理平台的需求，实现20:1的压缩倍数。最后，采用Quartus II和ModelSim进行编译和仿真，并在ALTERA公司的Stratix III的验证版上进行验证，与MATLAB计算结果进行比较，实现了正确的功能。小波变换模块的最高工作频率达到97.64MHZ，FPGA的逻辑资源使用率仅为1%；整个JPEG2000压缩系统的工作频率为89.53MHZ，FPGA逻辑资源使用率为54%，满足实际项目中对1280*720p60Hz图像20:1的压缩要求。
[Abstract]:In the high performance video monitoring system , taking into account the transmission bandwidth , the limitation of the external storage space and the lossless acquisition of the special occasion image , it is required that the acquisition end can carry out lossless compression transmission on the image data . Based on the video monitoring and processing platform of a company , the JPEG 2000 image compression system is realized by using FPGA . 1 . The whole compression system is divided into a preprocessing module , a component transformation module , a wavelet transform module , a series quantization module , a Tier 1 encoder and a Tier 2 encoder module by adopting a modular design mode on the FPGA structure of the JPEG 2000 compression system . 2 . In the wavelet transform module : according to the requirement of realizing the lossless compression , a 5 / 3 discrete wavelet is adopted , and a mapping structure is adopted to replace the normal multiplication operation according to the characteristics of the lifting coefficient in the wavelet transform , the delay of the key path is reduced , the conversion speed is improved , and the one - dimensional wavelet transformation is realized by using the three - stage pipeline according to the splitting , prediction and updating characteristics of the lifting step , and the hardware resources and the speed are optimized . 3 . The encoder module comprises a bit plane coding and an arithmetic coding , the design of the bit plane encoder adopts a channel parallel scheme , in the implementation mode of the arithmetic encoder , the coding efficiency of the encoder is improved by adopting an adaptive binary arithmetic coding and a five - stage pipeline mode . Finally , QuartusII and ModelSim are compiled and simulated , and verified by ALTERA company ' s x III verification , and the correct function is realized . The maximum operating frequency of the wavelet transform module is 97.64MHZ , the utilization rate of FPGA is only 1 % , the operating frequency of the whole JPEG 2000 compression system is 89.53MHZ , the utilization rate of FPGA logic resources is 54 % , which can meet the compression requirements of 1280 * 720p60 Hz image 20 : 1 in the actual project .

【学位授予单位】：华南理工大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN948.6;TN919.81

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