10GHz自适应锁相技术的研究

发布时间：2018-01-08 14:13

本文关键词：10GHz自适应锁相技术的研究　出处：《电子科技大学》2014年硕士论文　论文类型：学位论文

【摘要】：锁相技术自被提出以来,以其优越的性能优势广泛被应用于各个领域。模拟锁相环拥有高频、频谱特性好等数字锁相环不具有的优势,而近年提出的自适应锁相技术还克服了传统模拟锁相环压控振荡器输出振荡频率会出现较大相位瞬变的缺点,因此该技术在高品质振荡器技术方面正得到广泛应用。本文研究的自适应锁相技术,与传统的锁相系统利用参考信号与压控振荡器输出对比进行鉴相不同,该方法先对压控振荡器输出的信号经过放大后,再按一定比例分成两部分进行处理,最后进行鉴相。其中一部分信号通过使用外差法的高载波抑制组件进行处理,得到低噪声误差信号,输入到作为鉴相器的二极管双平衡混频器的射频端口,而另一部分信号通过可变移相器,其相位被调节到与射频端口信号相位相差90°后输入到混频器的本振端口。两路信号混频之后输出一个电平,该电平能够准确反应压控振荡器的输出频率与被锁参考信号的频率偏移。该电平信号被环路滤波器滤除高频部分后,得到一个电压近似与频率偏移成线性关系的低频信号。该信号与一可调直流偏压通过加法器合成后得到压控振荡器的调谐电压后送入压控调谐端完成锁相。该方法所使用的鉴相器是高性能二极管混频器,因此其调幅和调相噪声相对于压控振荡器的噪声低,可忽略不计。系统的相位噪声主要来自放大器、高载波抑制的组件和移相器。本文基于上述理论对锁相系统进行了设计和仿真,并对系统中需要使用的关键部件如压控振荡器、定向耦合器、移相器、混频器、加法器、环路滤波器等进行了制作和测试,最后将这些器件指标代入锁相环路模型完成了仿真和相位噪声的计算。仿真结果表明系统是稳定的,计算出的相位噪声也优于传统锁相技术的实现结果,初步证明了自适应锁相技术的可行性。
[Abstract]:Since it was proposed, PLL has been widely used in various fields because of its superior performance advantages. Analog PLL has the advantages of high frequency, good spectrum characteristics and other digital PLL does not have the advantages. The adaptive phase-locked technique proposed in recent years also overcomes the shortcoming of the traditional analog phase-locked loop voltage-controlled oscillator that the frequency of output oscillation will be large phase transient. Therefore, this technology is widely used in high quality oscillator technology. The adaptive phase-locking technology studied in this paper is different from the traditional phase-locked system using reference signal and VCO output to detect phase. This method first amplifies the output signal of the VCO and then divides it into two parts according to a certain proportion. Some of the signals are processed by using the high carrier suppression component of the heterodyne method to get the low noise error signal and input to the RF port of the diode dual balance mixer as the phase discriminator. The other part of the signal is controlled by a variable phase shifter whose phase is adjusted to the local oscillator port of the mixer after the phase difference between the phase of the radio frequency port and the radio frequency port signal is 90 掳, and a level is output after the two signals are mixed. The level can accurately reflect the deviation of the output frequency of the voltage controlled oscillator from the frequency of the locked reference signal, which is filtered out of the high frequency part by the loop filter. A low frequency signal with a linear relationship between voltage and frequency offset is obtained. The signal is synthesized with an adjustable DC bias through adder to obtain the tuning voltage of the voltage-controlled oscillator and then sent to the voltage-controlled tuning terminal to complete the phase-locking. The phase discriminator is a high performance diode mixer. Therefore, the noise of amplitude modulation and phase modulation is lower than that of voltage-controlled oscillator. The phase noise of the system is mainly from the amplifier. High carrier suppression components and phase shifters. Based on the above theory, this paper designs and simulates the phase-locked system. The key components of the system such as VCO, directional coupler, phase shifter, mixer are designed and simulated. The adder and loop filter are fabricated and tested. Finally, the simulation and phase noise calculation are completed by inserting these device parameters into the PLL model. The simulation results show that the system is stable. The calculated phase noise is also better than that of the traditional phase-locked technique, which proves the feasibility of the adaptive phase-locked technique.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN911.8

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