无线通信系统中流水线模数转换器的低成本低功耗研究与设计

发布时间：2018-01-10 03:18

本文关键词：无线通信系统中流水线模数转换器的低成本低功耗研究与设计　出处：《复旦大学》2014年硕士论文　论文类型：学位论文

【摘要】：无线通信技术的高速发展使各种手持终端通过移动互联网进行着大量的数据交换,改变着人们交流、思考、生活的方式。无线通信系统物理层的实现需要低功耗、低成本、高性能的集成电路设计。而在一个无线通信芯片中,模数转换器占用重要的位置,对于整个系统性能功耗的影响至关重要。本论文主要对应用在无线通信系统中的模数转换器进行研究,完成了一个10比特精度,50MHz采样频率的流水线型模数转换器的设计,重点研究了流水线型模数转换器中降低功耗和面积的相关技术,以及影响系统性能精度的主要原因,给出了电路实现的方案及仿真结果。本设计运用了以下技术减小模数转换器功耗和面积,改善模数转换器性能：整个模数转换器采用每级1.5bit级间运放共享结构和逐级缩放技术,减小了系统功耗和面积；在3.3V电压域设计运放,用薄栅器件优化套筒式增益提升运放,减小运放功耗和面积；使用耗尽型MOS管设计增益提升运放中的辅助运放,减小运放功耗；用耗尽型MOS管改进的CMOS开关替代栅压自举开关减小开关面积；优化时钟策略减小运放共享开关带来的误差,从而提高整个ADC的精度。该模数转换器采用华虹NEC 0.13μm1P6M CMOS工艺,ADC核心版图面积仅为0.2mm2,功耗为45mW;在50MHz采样频率,11 MHz输入信号下,SFDR达到78dB, SNDR达到60.7dB,有效位数达9.8bit。
[Abstract]:With the rapid development of wireless communication technology, various handheld terminals are exchanging a lot of data through the mobile Internet, changing people's communication and thinking. The realization of physical layer of wireless communication system requires low power, low cost, high performance integrated circuit design. In a wireless communication chip, A / D converter occupies an important position. It is very important to influence the power consumption of the whole system. In this paper, the ADC used in wireless communication system is studied, and a 10-bit precision is achieved. The design of pipeline analog-to-digital converter with 50MHz sampling frequency is presented. The related techniques to reduce power consumption and area in pipeline type A / D converter are studied, and the main reasons that affect the performance accuracy of the system are also discussed. The circuit implementation scheme and simulation results are given. The following techniques are used to reduce the power consumption and area of the ADC. Improve the performance of A / D converter: the whole A / D converter adopts the sharing structure of each stage 1.5 bit operation amplifier and step by step scaling technology, which reduces the power consumption and area of the system; The operational amplifier is designed in the voltage range of 3.3 V, and the sleeve gain is optimized with thin gate device to reduce the power consumption and area of the amplifier. A depleted MOS transistor is used to design the gain to enhance the auxiliary operational amplifier in the operational amplifier to reduce the power consumption of the operational amplifier. The improved CMOS switch of depleted MOS tube is used instead of the gate voltage bootstrap switch to reduce the switching area. The precision of the whole ADC is improved by optimizing the clock strategy to reduce the error caused by the operation amplifier shared switch. The ADC adopts the Huahong NEC 0.13 渭 m 1P6M CMOS process. The core layout area of ADC is only 0.2mm-2, and the power consumption is 45mW; At 50MHz sampling frequency and 11 MHz input signal, the SFDR is 78 dB, the SNDR is 60.7 dB, and the effective bit is 9.8 bits.
【学位授予单位】：复旦大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN92;TN792

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