QC-LDPC码的编译码器设计

发布时间：2018-01-14 00:17

本文关键词：QC-LDPC码的编译码器设计　出处：《哈尔滨工业大学》2014年硕士论文　论文类型：学位论文

更多相关文章： QC-LDPC EG-LDPC 最小和译码 FPGA

【摘要】：LDPC码是上世纪60年代问世，90年代兴起的一种性能接近香农限的编码方式。目前它的编码、译码、性能测试理论已经相当成熟，为了能够更好的实际应用对它的研究转移到了硬件实现上。而QC-LDPC码在保证了误码性能优异的同时，又由于它的准循环结构使得编译码简单，，从而成为在硬件实现上的适宜码字。对于QC-LDPC码的构造多数是采用基于欧几里德空间EG-LDPC码或基于均匀不完全区组的BIBD-LDPC码，这两种码字各有优点。EG-LDPC码的主要优点是码距比较大，构造方式灵活。本文为了突出设计的译码器能够处理码长长、码重大的LDPC码，构造的是基于EG (3,23)空间的码长4599，信息位长4227的LDPC码。这种码字在106量级的误码率距香农极限仅不到1dB。 QC-LDPC码的编码器相比随机方式形成的LDPC码硬件实现简单。文中主要介绍了如何构造具有准循环形式的生成矩阵，并按照并行、串行编码给出了三个不同的编码器，并说明了如何由这三种编码器结构资源消耗和编码速度设计出更多的编码器。最后FPGA实现是用串行编码方式。译码器的主要性能参数是吞吐量和误码率，对于FPGA实现还要考虑资源消耗的问题。本文基于最小和译码算法设计了一种并行的层型译码结构的译码器，由于校验节点处理器的个数可以任意选，当校验节点处理器选择8个时，译码吞吐量是可以达到1.6G bps左右。误码率也与软件仿真出的性能图差距仅0.4dB，资源消耗也仅不到10%。硬件实现平台上所采用的FPGA是XILINX的XC5VLX155T，软件版本是ISE14.4。
[Abstract]:LDPC code is a kind of coding method whose performance is close to Shannon's limit which emerged in the 1990s. At present, the theory of coding, decoding and performance testing is quite mature. In order to be able to better practical applications, the research on it is transferred to the hardware implementation. But QC-LDPC code not only ensures the excellent performance of the error code, but also makes the encoding and decoding simple because of its quasi-cyclic structure. So it becomes the suitable code word in the hardware implementation. For the construction of QC-LDPC codes, most of them are based on Euclidean space EG-LDPC codes or BIBD-LDPC codes based on uniform incomplete block. The main advantages of EG-LDPC codes are that the length of the code is large and the construction is flexible. In order to highlight the design of the decoder can deal with the length of the code, the code of LDPC code. The code length is 4599 and the information bit length is 4227, which is based on EG ~ (3 ~ (3) ~ (3)) space. The error rate of this code is less than 1 dB from Shannon's limit at 106th order of magnitude. The encoder of QC-LDPC code is easier to realize than the random LDPC code. In this paper, we mainly introduce how to construct the generation matrix with quasi-cyclic form, and according to the parallelism. Three different encoders are given in serial coding, and how to design more encoders by the resource consumption and coding speed of these three encoders is explained. Finally, FPGA is implemented by serial coding. The main performance parameters of the decoder are throughput and bit error rate, and the problem of resource consumption should be considered for the implementation of FPGA. In this paper, a parallel layer decoding decoder based on minimum sum decoding algorithm is designed. Since the number of check node processors can be selected arbitrarily, when the check node processor selects 8. The decoding throughput can reach about 1.6G bps, and the error rate is only 0.4dB from the performance diagram simulated by the software. The FPGA used on the hardware implementation platform is XC5VLX155T of XILINX, and the software version is ISE14.4.
【学位授予单位】：哈尔滨工业大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN911.22

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