HEVC中的DCT硬件架构设计与HLS实现研究

发布时间：2018-01-15 12:31

本文关键词：HEVC中的DCT硬件架构设计与HLS实现研究　出处：《西安电子科技大学》2014年硕士论文　论文类型：学位论文

【摘要】：ITU-T和ISO/IEC于2013年1月发布了一项新的视频压缩标准—HEVC。HEVC是继H.264之后的新一代视频压缩标准,与H.264相比,HEVC的压缩效率高出一倍,HEVC标准的出现解决了视频分辨率更高、视频数据量更大、存储和传输变得更加困难等难题。DCT变换在图像视频压缩领域的应用非常广泛,作为视频图像压缩的必要环节,DCT算法是图像视频编码算法中最活跃的研究部分之一。HEVC标准中的DCT变换是非常重要的预压缩过程,由于HEVC标准中需要对视频序列预测多个方向,然后通过压缩反馈获得最佳预测方向,因此需要多次执行DCT部分,所以DCT的高效实现显得十分重要。另外,HEVC对于整幅图像有更为灵活的分块机制,其中大尺寸的分块也会为相应尺寸的DCT变换带来不便,因此对大尺寸DCT变换的硬件实现研究显得尤为迫切。本文主要介绍了HEVC视频压缩编码流程中的DCT变换过程,并针对HEVC中DCT的大尺寸计算这一点,完成了两种DCT硬件架构的设计及HLS(High-level Synthesis)实现。本文的主要工作成果有:提出了以下两种硬件架构(1)基于矩阵相乘的DCT硬件架构及实现。根据资源利用率、处理延迟以及数据吞吐率这三个指标由HLS方法进行综合实现和优化,使得综合结果达到了5.56Gsps的数据吞吐率,满足了4K视频实时传输吞吐率。(2)基于蝶形算法的DCT硬件架构及实现。根据蝶形算法的运算原理,本文采用HLS方法对其进行了设计实现,与已有论文中DCT硬件结构实现结果进行了比较和分析。并以处理延迟以及数据吞吐率作为优化目标进行HLS优化设计,所完成的实现综合结果获得了6.77Gsps的数据吞吐率,比已有文献的实现结果相比获得了更高的数据吞吐率,且该实现可以应用于8K视频实时压缩。本文重点研究了HEVC中的整数DCT变换算法架构设计、HLS实现及其关键技术。在设计过程中解决了资源利用率过高、处理延迟过大和数据吞吐率无法达到目标值等问题;同时采用HLS方法完成了硬件实现,解决了传统硬件开发周期过长的问题,并且能够在一个软件设计上不断迭代出新的应用在不同场景中的硬件架构。最后对上述HLS实现分别完成了RTL功能仿真测试。其中,本文提出的硬件架构和HLS实现方法可广用于4K或8K分辨率视频的实时压缩。
[Abstract]:ITU-T and ISO/IEC in January 2013 released a new video compression standard - HEVC.HEVC H.264 is the second after the new generation of video compression standard, compared with H.264, HEVC compression efficiency is twice as high, HEVC standard solution with high resolution video, video data, storage and transmission become more difficult the problem of.DCT transform is widely used in the field of image and video compression, as a necessary part of video image compression, DCT algorithm is the DCT transform image encoding algorithm in the most active part of the research in.HEVC standard is very important to pre compression process, due to the need to predict the multiple directions of video sequence HEVC standard. Then through the feedback to obtain the best prediction direction compression, so you need DCT part of the implementation of many times, so the efficient implementation of DCT is very important. In addition, HEVC for the whole image is more flexible Block mechanism, the large size of the block will also bring inconvenience to the corresponding size of the DCT transform, so the large size DCT transform hardware research and implementation is particularly urgent. This paper mainly introduces the HEVC video compression encoding process of DCT transform process, and for the HEVC DCT in large size calculation of this point complete the design of two kinds of DCT and HLS hardware architecture (High-level Synthesis). The main contributions of this dissertation are: put forward the following two kinds of hardware architecture (1) and the realization of DCT hardware architecture based on matrix multiplication. According to the resource utilization rate, processing delay and throughput of the three indicators by the method of integrated HLS the implementation and optimization, makes the comprehensive results reached 5.56Gsps data throughput to meet the 4K real-time video transmission throughput. (2) and the realization of DCT hardware architecture based on butterfly algorithm. According to the operation principle of butterfly algorithm in this paper. The HLS method has carried on the design and implementation of DCT hardware structure, the existing results are compared and analyzed. And the processing delay and data throughput as the optimization goal for HLS optimization design, to achieve comprehensive results the obtained 6.77Gsps data throughput rate than the published results obtained and compared a higher data throughput, and the implementation of 8K can be applied to real-time video compression. This paper focuses on the architecture of integer DCT transform algorithm in HEVC design, HLS implementation and its key technology. In the design process to solve the resource utilization rate is too high, excessive processing delay and data throughput can reach the target value. At the same time; using HLS method to complete the hardware implementation, to solve the traditional hardware development cycle is too long, and can in a software design iteration of new applications in the same The hardware architecture of the scene. Finally, the RTL function simulation test is completed for the above HLS implementation. The hardware architecture and HLS implementation method proposed in this paper can be widely used for real-time compression of 4K or 8K resolution video.

【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN919.81

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