视频压缩系统中算术编码器的VLSI设计

发布时间：2018-01-18 05:07

本文关键词：视频压缩系统中算术编码器的VLSI设计　出处：《西安电子科技大学》2014年硕士论文　论文类型：学位论文

更多相关文章： CABAC VLSI设计 H.264 编码器

【摘要】：信息科技的不断发展,使得当今社会对于高品质信息生活的需求不断提高。高分辨率的视频越来越受到用户的欢迎。但是,在一段时间内,对于视频传输来说,带宽都是有限的,因此,如何在有限的带宽中传输尽可能高品质的视频在如今是一个非常有价值的课题。在这个课题中,最关键的就是高效率的视频压缩技术。H.264标准是一个简洁、高效的视频压缩标准。该标准通过更加复杂而有效的算法,大大的提高了视频压缩的效率。在这些算法中,处于后端的熵编码算法在提高视频压缩编码效率的过程中起着非常重要的作用。H.264标准中有两种熵编码算法:CAVLC将上下文元素引入到可变长熵编码算法中,减少了编码的冗余量,提高了编码的效率。CABAC建立在算术编码的基础上,它的思想不再是对单个字符进行编码,而是对一长串码流进行编码,以算法上的复杂度为代价来换取编码效率的提升,大大的提高了编码效率。目前,算术编码思想已经成为未来熵编码算法的主体思想。随着目前高速率的FPGA芯片的不断的发展,CABAC的算法复杂度在如今的FPGA平台是可以满足的,所以我们可以在现有的FPGA平台上来实现一个处理CABAC的熵编码系统。本文从H.264标准出发,首先分析了视频数据在熵编码之前所流经的几道处理程序:帧内预测或帧间预测、DCT变换与量化等;随后着重研究了H.264中的熵编码算法CABAC,通过从多进制算术编码到二进制算术编码的改进思路的探索,理解了CABAC的相关算法思想,在此基础上重点研究了CABAC的算法原理和组成部分,并根据其组成部分的特点设计相应的模块。本文所设计的算术编码器将整个系统分为四个部分,分别为宏块编码序列模块、宏块上下文管理模块、语法元素二值化模块与二进制算术编码模块。其中,宏块编码序列模块中所进行的是对当前宏块各语法元素进入编码器的顺序的管理,宏块上下文管理模块记录的是周围相关宏块的信息,语法元素二值化模块主要针对的是H.264中不同语法元素的二值化,二进制算术编码模块主要进行的是初始化过程,为相应的语法元素找到概率模型并进行算术编码,同时,在二进制算术编码的初始化过程中,引进流水线技术来提高系统的工作效率。设计完相应的模块后,利用modelsim来搭建仿真平台来对各模块进行仿真,最后选择Xilinx公司Virtex-6系列中型号为XC6VLX365T的FPGA芯片来搭建平台,并对1280x1024@25f的视频源进行压缩编码。在这种情况下,编码器的最大时钟可以达到99.732MHZ,高于实时编码过程中的最大码率,能够实现在一个时钟周期内编码一个字符的操作。因此,该编码器能够实现对该分辨率的视频的实时熵编码过程。
[Abstract]:With the continuous development of information technology, the demand for high-quality information life is increasing. High-resolution video is more and more popular with users. However, for a period of time, for video transmission. Bandwidth is limited, therefore, how to transmit the highest quality video in the limited bandwidth is a very valuable topic nowadays. The most important is that the highly efficient video compression technology. H. 264 is a simple and efficient video compression standard, which uses more complex and effective algorithms. Greatly improve the efficiency of video compression. In these algorithms. The entropy coding algorithm at the back end plays a very important role in improving the efficiency of video compression coding. There are two entropy coding algorithms in H.264 standard:. CAVLC introduces context elements into the variable length entropy coding algorithm. The redundancy of coding is reduced, and the efficiency of coding is improved. CABAC is based on arithmetic coding. Its idea is not to encode a single character, but to encode a long stream of bits. At the cost of the complexity of the algorithm in exchange for the improvement of coding efficiency, greatly improve the coding efficiency. The idea of arithmetic coding has become the main idea of entropy coding algorithm in the future. With the development of FPGA chip with high speed at present. The computational complexity of CABAC can be satisfied in today's FPGA platform. So we can implement an entropy coding system to deal with CABAC on the existing FPGA platform. Firstly, several processing programs that video data pass through before entropy coding are analyzed: intra prediction or inter prediction DCT transform and quantization etc. Then, the entropy coding algorithm in H.264 is studied, and the related algorithm of CABAC is understood through the exploration of the improved idea from multi-ary arithmetic coding to binary arithmetic coding. On this basis, the principle and components of the algorithm of CABAC are studied, and the corresponding modules are designed according to the characteristics of the components. The arithmetic encoder designed in this paper divides the whole system into four parts. They are macro block coding sequence module, macro block context management module, syntax element binarization module and binary arithmetic coding module. In the macroblock coding sequence module, the order in which each syntax element of the current macroblock enters the encoder is managed, and the macroblock context management module records the information about the surrounding macroblock. The binarization module of syntax elements is mainly aimed at the binarization of different syntax elements in H.264, and the binary arithmetic coding module mainly carries on the initialization process. At the same time, in the initialization process of binary arithmetic coding, pipeline technology is introduced to improve the efficiency of the system. Using modelsim to build a simulation platform to simulate each module. Finally, we choose the FPGA chip of Virtex-6 series of Xilinx Company as XC6VLX365T to build the platform. In this case, the maximum clock of the encoder can reach 99.732MHZ, which is higher than the maximum bit rate in the real-time coding process. The encoder can encode a character in a clock cycle. Therefore, the encoder can realize the real-time entropy coding process for the video of the resolution.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN919.81

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