FPGA与PC间基于PCIe和千兆以太网的通信设计

发布时间：2018-01-20 03:25

本文关键词： 高速接口 PCIe WinDriver 千兆以太网口 Winpcap　出处：《西安电子科技大学》2014年硕士论文　论文类型：学位论文

【摘要】：随着系统性能、功能和带宽的提高,高速数据采集与记录以及其他数据处理的数据吞吐量都日益增长。因此通过研究发展新的高速接口技术来解决带宽限制和高速传输这些关键问题是一种必然趋势和迫切的需求。FPGA已发展成为实现数字系统的主流平台之一,广泛应用于信号处理及通信等各个领域。FPGA在信号处理时可并行运行,处理速度快,但不适合实现高精度复杂的运算处理。而PC计算机具备相当强大的计算和数据处理能力,所以通常情况下会将需要进行高精度复杂的计算交由计算机负责处理。这就涉及到FPGA与PC间进行大量数据的传输问题,因此构建PC机与FPGA的高速数据传输系统成为当前的研究趋势。本文根据当前研究趋势和实际科研项目要求,对PCIe和千兆以太网进行了深入研究,并设计了PCIe DMA数据传输系统和千兆以太网数据传输系统来实现FPGA与PC机之间的数据通信。本文的具体工作如下:1.深入研究PCIe和千兆以太网,了解PCIe和千兆以太网的技术优势,具体分析PCIe和千兆以太网的传输协议,详细说明PCIe TLP数据包格式和以太网标准数据帧格式。2.完成PCIe DMA数据传输系统设计。设计方案主要包括两大部分,分别是FPGA端Verilog逻辑模块开发以及PC端的驱动和C应用程序开发。FPGA端基于PCIe IP Core完成了发送接收引擎模块、寄存器读写控制模块和FIFO读写控制模块的设计。定义了相应模块的接口,并分析了数据传输的时序。PC端采用WinDriver进行PCIe的驱动开发,并根据WinDriver提供的驱动API函数完成C应用程序的设计。3.完成千兆以太网数据传输系统设计。设计方案也主要包括两大部分,分别是FPGA端Verilog逻辑模块开发以及PC端Winpcap应用程序开发。FPGA端基于嵌入式三态以太网MAC IP Core,设计了发送接收引擎模块、FIFO读写控制模块和物理接口模块。定义了相应模块的接口,并分析了数据传输经过LocalLink接口和Client用户接口上的传输时序。PC端采用Winpcap提供的网络编程完成了C应用程序的设计,实现了捕获FPGA端发送的数据包以及发送原始数据包至FPGA端的功能。4.PCIe DMA数据传输系统和千兆以太网数据传输系统在Xilinx ML507开发板上进行了性能测试。记录FPGA与PC间进行读写测试的结果,验证这两个系统的可用性和稳定性,最后分析了影响系统传输速率的原因以及系统目前仍存在的不足。本文设计的PCIe DMA数据传输系统和千兆以太网数据传输系统基本实现了FPGA与PC间大量数据的快速传输,对后续科研做出了一定的贡献。
[Abstract]:With the improvement of system performance, function and bandwidth. The data throughput of high speed data acquisition and recording and other data processing is increasing, so it is an inevitable trend to solve the key problems of bandwidth limitation and high speed transmission by researching and developing new high speed interface technology. FPGA has become one of the mainstream platforms to realize digital system. FPGA is widely used in various fields such as signal processing and communication. FPGA can run in parallel in signal processing, and the processing speed is high. But it is not suitable for high precision and complex operation, and PC computer has quite powerful computing and data processing ability. Therefore, the computer is usually responsible for the complex computation with high accuracy, which involves a large amount of data transmission between FPGA and PC. Therefore, the construction of high-speed data transmission system between PC and FPGA has become the current research trend. According to the current research trend and the requirements of the actual scientific research projects, PCIe and Gigabit Ethernet have been deeply studied in this paper. PCIe DMA data transmission system and gigabit Ethernet data transmission system are designed to realize the data communication between FPGA and PC. 1. Deeply study PCIe and Gigabit Ethernet. Understand the technical advantages of PCIe and Gigabit Ethernet, and analyze the transport protocols of PCIe and Gigabit Ethernet. The PCIe TLP data packet format and Ethernet standard data frame format. 2. Complete the design of PCIe DMA data transmission system. The design scheme mainly includes two parts. Verilog logic module development of FPGA, driver of PC and C application development. FPGA-based sending and receiving engine module based on PCIe IP Core. The design of register read-write control module and FIFO read-write control module. The interface of the corresponding module is defined. And analyze the timing of data transmission. PC end using WinDriver to develop the driver of PCIe. According to the driver API function provided by WinDriver, the design of C application program is completed. 3. The design of gigabit Ethernet data transmission system is completed. The design scheme mainly includes two parts. The development of Verilog logic module in FPGA terminal and Winpcap application program in PC terminal. FPGA-based MAC IP Core based on embedded three-state Ethernet. Designed the sending and receiving engine module FIFO read and write control module and physical interface module, and defined the interface of the corresponding module. And analyzed the data transmission through the LocalLink interface and Client user interface transmission timing. PC end using network programming provided by Winpcap to complete the design of C application program. The function of capturing the data packets sent by the FPGA side and sending the original data packets to the FPGA side. 4. PCIe. DMA data transmission system and gigabit Ethernet data transmission system are tested on the Xilinx ML507 development board, and the results of reading and writing test between FPGA and PC are recorded. Verify the availability and stability of the two systems. Finally, the paper analyzes the reasons that affect the transmission rate of the system and the shortcomings of the system at present. The PCIe designed in this paper. DMA data transmission system and gigabit Ethernet data transmission system basically realize the fast data transmission between FPGA and PC. It has made a certain contribution to the follow-up scientific research.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN915.02

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