CPFSK调制解调器设计与实现

发布时间：2018-01-27 04:27

本文关键词： m序列 RS码交织码卷积码 Viterbi译码 CPFSK FPGA　出处：《南京理工大学》2014年硕士论文　论文类型：学位论文

【摘要】：本文主要设计实现了CPFSK调制解调通信系统,系统中包含m序列加密解密电路、RS编译码电路、交织与解交织电路、卷积编译码电路以及CPFSK调制解调电路。文中首先设计了系统的总体框图,然后对系统中的各个电路的设计与实现作了深入的研究。在系统的加密部分中,本文基于m序列设计32级m序列加密解密电路,并在FPGA的硬件基础上,采用Verilog语言实现了32级m序列加密解密电路；在系统的纠错码中,采用了RS(255,239)码与(2,1,7)卷积码级联的方式,并在两编码器的级联中间插入了交织器,以提高纠错系统的纠错性能；对于RS(255,239)码的编码电路,本文对其传统的编码算法进行了改进,并在FPGA的硬件基础上,采用Verilog语言实现了RS(255,239)编码电路,并基于Altera的IP核实现了RS(255,239)码的译码电路；在研究RS编译码电路中,还研究了电路工作过程中遇到的码率匹配问题和串并转换问题,并提出了该问题的解决方案,在FPGA的硬件基础上,采用Verilog语言设计实现了码率匹配电路和串并转换电路；交织器本文采用卷积交织的方法来实现,并在FPGA的硬件基础上,采用Verilog语言实现了交织与解交织电路；对于(2,1,7)卷积码的编码电路,本文在FPGA的硬件基础上,采用Verilog语言实现了(2,1,7)卷积编码电路,而(2,1,7)卷积码的译码电路,本文采用Viterbi译码算法来实现,并基于Altera的IP核实现了Viterbi译码电路；最后,CPFSK调制解调电路采用了其特殊的一种方式MSK调制,采用Verilog语言设计实现了MSK经典的正交调制电路,并在DFT算法的基础上,设计了一种更加简单有效的MSK解调方案,采用Verilog语言实现了该解调电路。在硬件实现的同时,本文还在Matlab平台上对各个模块进行了仿真验证,确保电路设计的正确性。
[Abstract]:This paper mainly designs and implements the communication system of CPFSK modulation and demodulation, which includes m sequence encryption and decryption circuit, RS encoding and decoding circuit, interleaving circuit and deinterleaving circuit. Convolution encoding and decoding circuit and CPFSK modulation and demodulation circuit. In this paper, the overall block diagram of the system is first designed, and then the design and implementation of each circuit in the system are deeply studied. In the encryption part of the system. In this paper, a 32-level m sequence encryption and decryption circuit is designed based on m sequence. Based on the hardware of FPGA, the 32-level m sequence encryption and decryption circuit is implemented by Verilog language. In the error correction code of the system, the scheme of concatenation of RSH255N239) code and the convolutional code of 2H2P1H7) is adopted, and an interleaver is inserted between the concatenations of the two encoders. To improve the error-correcting performance of the system; In this paper, the traditional coding algorithm is improved and based on the hardware of FPGA, the encoding circuit of RSH255N239) code is improved. The RSF255P239) coding circuit is realized by using Verilog language, and the decoding circuit of RSH255P239) code is realized based on the IP core of Altera. In the research of RS codec circuit, the rate matching problem and the serial-parallel conversion problem encountered in the working process of the circuit are also studied, and the solution to this problem is put forward, based on the hardware of FPGA. The bit-rate matching circuit and the series-parallel conversion circuit are designed and implemented by using Verilog language. The Interleaver is implemented by convolution interleaving method, and based on the hardware of FPGA, the interleaving and deinterleaving circuits are implemented by Verilog language. On the basis of the hardware of FPGA, this paper uses Verilog language to realize the coding circuit of the convolutional code. 7) the decoding circuit of convolutional code is realized by Viterbi decoding algorithm, and the Viterbi decoding circuit is implemented based on IP core of Altera. Finally, the CPFSK modulation and demodulation circuit adopts its special way of MSK modulation, and the MSK classic quadrature modulation circuit is designed and implemented by Verilog language. On the basis of DFT algorithm, a more simple and effective MSK demodulation scheme is designed. The demodulation circuit is realized by Verilog language. In order to ensure the correctness of the circuit design, the simulation of each module is carried out on the Matlab platform.
【学位授予单位】：南京理工大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN915.05

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