面向密码应用FPGA高级综合关键技术研究

发布时间：2018-02-09 16:43

本文关键词： FPGA 高性能计算高级综合密码应用 IP核模板库　出处：《国防科学技术大学》2014年博士论文　论文类型：学位论文

【摘要】：高性能计算正经历着根本性的变化。能耗和散热的需求也逐渐成为限制了大型数据中心的不断扩张的瓶颈。这些变化推动着高性能计算不断发展新的计算技术。可编程逻辑阵列技术是一项能够在提高性能的同时降低能耗技术。但是FPGA开发面临多重挑战,在硬件上开发并行的应用程序,超过了许多现有开发人员的知识,因而我们需要更加方便地编程工具来挖掘FPGA的高性能计算潜力。高级综合是项将高级语言的描述转换成硬件结构的行为描述的技术。本文提出了基于数据驱动的应用类IP核高级综合的设计方法。课题从实际出发,设计一个可以实现的系统框架,而且要保证这个系统不仅使用方便,还能够生成出高性能的加密硬件代码。根据用户的模块化描述,生成软件流程图。将加密算法实现成为FPGA可重构的参数化IP核,构建参数化的IP核库。通过搜索算法,根据软件流程图和IP核库,生成并优化硬件节点图。最后,根据硬件节点图,生成Verilog代码。本文构建了高效的IP核库,IP核的表示和实现是可重构加速器的硬件实现基础。我们利用数据结构来描述这些硬件IP核的属性和计算行为,为生成硬件流程图的搜索算法提供了IP核。本文将典型的密码算法通过硬件实现,并由此构建了面向密码应用的高性能加密模板库。另外,还针对程序的循环、分支和其他结构,设计了相应的参数化模块。本文研究了面向硬件结构的数据流图优化算法。根据前端生成的数据流图,利用硬件模块绑定算法生成硬件流图。面向基于模块的硬件流图,本文主要通过重用模块,以减少流水线的资源消耗;采用了公共子表达式消除,来优化分支结构;采用资源最佳算法来实现设计空间的探索。最后通过构建FPGA原型系统,验证了本文提出的高级综合框架。针对目标FPGA芯片对硬件系统的总体结构进行了设计。目标系统中高级综合生成的硬件代码与顶层控制模块一起集成到FPGA中,构成完整的FPGA实现。最后对多个应用程序的高级综合进行了示例,并进行性能实现对比,实验结果显示本文的高级综合框架及优化算法有着良好的效果。
[Abstract]:High performance computing is undergoing fundamental changes, and the demand for energy consumption and heat dissipation has gradually become a bottleneck that limits the continuous expansion of large data centers. These changes promote the development of new computing technologies for high performance computing. Programmable logic array technology is a technology that can improve performance while reducing energy consumption. But FPGA development faces many challenges. Developing parallel applications on hardware is beyond the knowledge of many existing developers, Therefore, we need more convenient programming tools to exploit the high performance computing potential of FPGA. Advanced synthesis is a technique to transform high-level language description into behavior description of hardware structure. The design method of applying IP-like core advanced synthesis. Design a system framework that can be implemented, and ensure that the system is not only easy to use, but also able to generate high-performance encryption hardware code. The encryption algorithm is realized as the FPGA reconfigurable parameterized IP core, and the parameterized IP core library is constructed. Through the search algorithm, the hardware node diagram is generated and optimized according to the software flow chart and the IP core library. According to the hardware node diagram, the Verilog code is generated. In this paper, the representation and implementation of IP core in an efficient IP core library is the basis of the hardware implementation of the reconfigurable accelerator. We use the data structure to describe the properties and computing behavior of these IP cores. The IP core is provided for the search algorithm to generate the hardware flow chart. This paper implements the typical cryptographic algorithm by hardware, and constructs a high-performance encryption template library for cryptographic application. In addition, the paper also aims at the cycle of the program. The corresponding parameterized modules are designed for branching and other structures. In this paper, the optimization algorithm of data flow diagram for hardware structure is studied. According to the data flow diagram generated by the front end, Hardware flow diagram is generated by hardware module binding algorithm. This paper mainly reuses module to reduce pipeline's resource consumption, adopts common subexpression elimination to optimize branch structure. The optimal algorithm of resources is used to explore the design space. Finally, the prototype system of FPGA is constructed. The overall structure of the hardware system is designed for the target FPGA chip. The hardware code generated by the advanced synthesis in the target system is integrated into the FPGA with the top-level control module. Finally, an example of advanced synthesis of multiple applications is given, and the performance comparison is carried out. The experimental results show that the advanced synthesis framework and the optimization algorithm of this paper have a good effect.
【学位授予单位】：国防科学技术大学
【学位级别】：博士
【学位授予年份】：2014
【分类号】：TN918.2;TN791

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