WIFI系统中QC-LDPC编码算法研究与FPGA实现

发布时间：2018-02-21 08:36

本文关键词： 低密度奇偶校验码准循环 Efficient编码算法现场可编程门阵列　出处：《电子科技大学》2014年硕士论文　论文类型：学位论文

【摘要】：LDPC码的全称是低密度奇偶校验码,它是线性分组码的一种,目前在通信领域得到了广泛的应用,为多种标准所采用。同Turbo码一样,它有着接近香农限的优异性能,并且LDPC码的误码率可以通过多次迭代译码的方法来有效地降低。LDPC码的校验矩阵具有稀疏特性,有利于简化编码时的计算复杂度,而QC-LDPC码则是通过对基础矩阵进行循环移位而得到的一种具有循环特性的LDPC码,这种循环特性使它减少了编译码过程中存储校验矩阵所需要的存储空间,进一步的简化了编译码的过程。本文所要实现的是基于WIFI系统的数据传输,需要较高的吞吐率与时钟频率,较低的误码率以及可接受的资源消耗。为解决这一问题,本文选择了QC-LDPC码的Efficient编码算法,并对该算法进行了硬件实现,最后给出了具体的硬件指标。在对线性分组码的相关概念进行介绍之后,本文简述了LDPC码的概念、分类以及编译码的基本原理。然后分析了通过生成矩阵进行编码的LDPC编码算法的复杂度,并与Efficient编码算法的复杂度进行了对比,前者复杂度为O(),后者为O(n)。基于系统的需求,本文选择了Efficient算法来进行LDPC码的编码。针对该算法,本文给出了QC-LDPC编码器的设计方案以及个子模块的电路结构,并对各模块进行了功能仿真。设计的编码器可以兼容四种码率,编码器顶层接口时序的正确性也通过功能仿真得到了验证。在进行测试与验证时,本文将编码器编码产生的码字与相关控制信息通过串口一起传回PC,通过Matlab来分析编码结果是否正确,以此完成验证过程。文中给出了验证平台中各模块的设计方案,最后得到了验证结果以及编码器所能达到的硬件指标本文所设计的QC-LDPC编码器达到了系统要求,最后实现的指标如下:输入位宽32bit;输出位宽96bit;稳定时钟频率200MHz,最高时钟频率250MHz,关键路径延迟为3.761ns;吞吐率为5Gbps;码长2304bit,码率为5/6时,在信噪比为3dB的情况下,通过BP译码算法进行译码后,所得的误码率为10-7,满足系统所提出的指标要求。
[Abstract]:The full name of LDPC code is low density parity check code. It is a kind of linear block code. It has been widely used in the field of communication and adopted by many standards. Like Turbo code, it has excellent performance close to Shannon limit. Moreover, the error rate of LDPC codes can be effectively reduced by multiple iterative decoding, which can reduce the sparse property of the check matrix of the. LDPC codes, which is helpful to simplify the computational complexity of the codes. The QC-LDPC code is a kind of LDPC code with cyclic property, which reduces the storage space needed to store the check matrix in the process of encoding and decoding. In order to solve this problem, the data transmission based on WIFI system needs high throughput and clock frequency, low bit error rate and acceptable resource consumption. In this paper, the Efficient coding algorithm of QC-LDPC code is selected, and the algorithm is implemented in hardware. Finally, the specific hardware specifications are given. After introducing the related concepts of linear block code, the concept of LDPC code is briefly described. Then, the complexity of LDPC coding algorithm based on generating matrix is analyzed and compared with that of Efficient coding algorithm. In this paper, Efficient algorithm is chosen to encode the LDPC code. For this algorithm, the design scheme of the QC-LDPC encoder and the circuit structure of the sub-module are given, and the functional simulation of each module is carried out. The encoder designed can be compatible with four code rates. The correctness of the timing of the top-level interface of the encoder is also verified by functional simulation. In this paper, the codewords generated by encoder coding and related control information are transmitted back to PCC through serial port, and the code result is analyzed by Matlab to complete the verification process. The design scheme of each module in the verification platform is given in this paper. Finally, the verification results and the hardware specifications of the encoder are obtained. The QC-LDPC encoder designed in this paper meets the requirements of the system. The results are as follows: input bit width 32 bit; output bit width 96 bit; stable clock frequency 200 MHz, maximum clock frequency 250 MHz, critical path delay 3.761 ns; throughput 5 Gbps. code length 2304 bit, code rate 5/6, when SNR is 3 dB, After decoding by BP decoding algorithm, the BER is 10 ~ (-7), which meets the requirements of the system.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN92;TN911.22

【共引文献】