基于包络脉宽和相位差分调制的低功耗数字型发送前级研究

发布时间：2018-02-21 23:24

本文关键词： 极坐标发射机双通路压控振荡器自动频率校正脉冲宽度调制　出处：《北京理工大学》2015年硕士论文　论文类型：学位论文

【摘要】：近年来,随着各种便携式无线通信产品的应用,可植入式医疗电子设备的兴起,以及无线体域网和无线个人网的迅猛发展,人们对发射机的功耗、效率以及设计复杂度提出了很高的要求;此外,高频谱效率和高数据传输率的发展趋势促使各种工作在不同频带的非常包络数据调制方式不断涌现,为了确保好的通道抑制和低的信号失真,人们对发射机又提出了高线性度、多模多带操作的要求。在实现这些目标的众多发射机技术中,极坐标是个不错的选择。本课题基于极坐标发射机的已有架构及其发展趋势,从数字型包络调制、全差分相位调制、简易的通路延时匹配等创新点入手,致力于为低功耗、低成本、高能效、高线性、多模多带发送前级提供可行的系统方案。相位通路采用Delta-Sigma差分调制双通路压控振荡器,实现基频数字相位到射频恒包络相位的搬移;压控振荡器采用分段偏置和全差分的混合方法来确保调制线性度,引入自动载频校正环路来维持载波频率。包络通路利用数字型脉冲宽度调制器驱动功率级反相器及LC滤波器,实现数字包络到模拟包络的转换,并为后续开关型功放提供大电流驱动;为了保证延时模块的精准性,引入单元延时自校准环路。论文首先就发射机研究的背景及意义进行了简单介绍;然后比较和分析了几种传统发射机和极坐标发射机的架构;之后提出了本课题所采用的极坐标发射机架构,并阐述了调制通路关键模块的实现方法。在UMC 180nm CMOS工艺条件、1.8V电源电压下进行了发射机电路设计和系统级仿真,完成了关键模块的版图实现。仿真结果显示,系统在400kHz频偏处的相位噪声为-124.9dBc/Hz,矢量误差幅度为4%,满足8PSK(EDGE)通信系统指标。
[Abstract]:In recent years, with the application of various portable wireless communication products, the rise of implantable medical electronic devices, and the rapid development of wireless body area network and wireless personal network, the power consumption of transmitters has been greatly increased. In addition, the development trend of high spectral efficiency and high data transmission rate has led to the emergence of a variety of extremely enveloped data modulation methods working in different frequency bands. In order to ensure good channel suppression and low signal distortion, high linearity and multimode multiband operation are required for transmitters. Polar coordinates are a good choice. Based on the existing structure of polar coordinate transmitter and its development trend, this paper starts with the innovations of digital envelope modulation, fully differential phase modulation, simple path delay matching, and devotes to low power consumption. Low cost, high energy efficiency, high linearity, multi-mode multi-band transmission front stage provides a feasible system scheme. The phase path uses Delta-Sigma differential modulation dual-channel voltage-controlled oscillator to realize the shift from the fundamental digital phase to the RF constant envelope phase. The VCO adopts a mixed method of piecewise bias and full difference to ensure the modulation linearity, and an automatic carrier frequency correction loop is introduced to maintain the carrier frequency. The envelope path uses a digital pulse width modulator to drive the power level inverter and LC filter. To realize the conversion of digital envelope to analog envelope, and to provide high current drive for subsequent switching power amplifier, to ensure the accuracy of delay module, The paper introduces the background and significance of transmitter research, and then compares and analyzes several traditional transmitters and polar coordinate transmitters. Then, the structure of polar coordinate transmitter used in this paper is put forward, and the realization method of the key module of modulation path is described. The transmitter circuit design and system-level simulation are carried out under the UMC 180nm CMOS technology condition of 1.8V power supply voltage. The simulation results show that the phase noise of the system is -124.9dBc / Hzat 400kHz frequency offset, and the vector error amplitude is 4, which meets the requirements of 8PSK / EDGE communication system.
【学位授予单位】：北京理工大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN832

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