快速自适应全数字锁相环的研究与设计

发布时间：2018-02-26 07:13

本文关键词： 全数字锁相环自适应比例积分控制复合控制 FPGA　出处：《南华大学》2014年硕士论文　论文类型：学位论文

【摘要】：本文研究了一种快速自适应全数字锁相环路，一方面，该系统采用了基于自适应的比例积分控制策略，环路带宽可以随输入信号频率的大小进行自动调节，因而具有较大的锁相范围；另一方面，环路滤波器参数可以根据鉴相误差的大小进行快捕区、缓冲区和锁定区的切换，即环路带宽可以随鉴相误差的大小进行自动调节，有效的克服了环路捕捉速度和抗噪声性能之间的矛盾。环路参数的实现则采用了数字移位相加的设计方法，较之传统采用除法器的实现方法，大大的简化了电路结构。整个锁相环均由数字模块构成，克服了模拟锁相环所固有的压控振荡器非线性、鉴相不精确、器件易饱和以及高阶不稳定等缺陷，使系统本身又具有参数稳定、可靠性高和易于集成等特点。在深入研究该锁相环理论模型和和实现结构的基础上，最终通过自顶向下的模块化设计技术对整个系统进行了电路设计，在QuartusII软件环境下进行了相关的综合仿真，并比较分析了该设计在不同环路控制参数作用下的各项性能，最后将设计程序下载到Altera公司的EP1C6Q240C8FPGA器件予以硬件实现。系统仿真与实测结果表明：采用自适应控制与动态比例积分控制相结合的复合控制方式，可使环路带宽随输入信号频率和鉴相误差的变化进行实时调节。当系统时钟为60MHz时，环路调节时间约为8个输入信号周期，超调量为4.32%，，跟踪锁定范围为40Hz-1MHz，系统各项性能和理论分析非常吻合。
[Abstract]:In this paper, a fast adaptive all-digital phase-locked loop is studied. On the one hand, the system adopts an adaptive proportional integral control strategy, and the loop bandwidth can be automatically adjusted with the input signal frequency. On the other hand, the parameters of the loop filter can be quickly captured according to the size of the phase discrimination error, and the switching between the buffer zone and the locking area, that is, the bandwidth of the loop can be automatically adjusted with the size of the phase discrimination error. The contradiction between the speed of the loop capture and the anti-noise performance is overcome effectively. The design method of digital shift and addition is used to realize the parameters of the loop, which is compared with the traditional implementation method of divider. The circuit structure is greatly simplified. The whole PLL is composed of digital modules, which overcomes the inherent defects of the analog PLL, such as nonlinear voltage controlled oscillator, inaccurate phase identification, easy saturation of devices and high order instability, etc. The system has the characteristics of stable parameters, high reliability and easy integration. On the basis of deeply studying the theoretical model and the realization structure of the PLL, the circuit design of the whole system is carried out through the top-down modular design technology, and the related comprehensive simulation is carried out under the environment of QuartusII software. The performances of the design under the action of different loop control parameters are compared and analyzed. Finally, the design program is downloaded to the EP1C6Q240C8FPGA device of Altera Company for hardware implementation. The system simulation and measured results show that the combination of adaptive control and dynamic proportional integral control is adopted. The loop bandwidth can be adjusted in real time with the change of input signal frequency and phase discrimination error. When the system clock is 60MHz, the loop adjusting time is about 8 input signal cycles. The overshoot is 4.32 and the tracking locking range is 40Hz-1MHz. The performance of the system is in good agreement with the theoretical analysis.
【学位授予单位】：南华大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN911.8

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