基于压缩感知的重构算法研究及其VLSI实现

发布时间：2018-02-26 20:01

本文关键词： 压缩感知子空间追踪算法最小二乘方程求解 VLSI　出处：《复旦大学》2014年硕士论文　论文类型：学位论文

【摘要】：压缩感知(c ompressive Sensing, CS)理论是近年来在信号处理领域新兴起的一门理论,该理论指出在信号满足稀疏性的情况下,能够以低于奈奎斯特(Nyquist)采样速率的速度对信号进行观测,只需要获取较少的数据点就能够通过重构算法精确的恢复信号,如此优越的特质使其有着广阔的应用前景,并得到了广泛的研究。重构算法研究是压缩感知理论的重要组成部分,国内外学者也进行了大量的研究,主要集中在三个方向,一类是凸优化算法、一类是贪婪算法、一类是组合算法。其中的贪婪算法,计算复杂度小、重构速度快、易于实现,使其更加利于实际应用。通过对不同的贪婪算法的仿真分析,本文在性能优越的子空间追踪算法(Subspace Pursuit, SP)基础上,综合考虑性能,重构时间和实现面积等因素,对算法进行了改进和优化,设计实现了一种重构算法加速器。将SP算法中的两次最小二乘操作优化为一次最小二乘操作,降低了计算复杂度和实现面积,并减小了重构时间,同时很好的保证了重构精确度。在具体的硬件实现过程中,矩阵取逆采用ACD(Alternative Cholesky Decomposition)算法,并将该算法设计成脉动阵列结构,从而提高了电路性能。对于硬件实现的复杂单元除法器,采用了移位和减法来代替,从而去除了关键路径延时,并减小了实现面积。通过复用ACD算法模块中的乘法器单元完成其他模块中的乘法操作进一步的减小了实现面积。本文设计的重构算法加速器,采用长度为64的观测信号,利用高斯随机分布矩阵,对信号长度为256、稀疏度为8的数字信号进行了重构,使用SMIC 65nm工艺对设计进行了综合,综合后的面积为2316K Gates,工作频率为222.2MHz。
[Abstract]:The theory of compressed ompressive sensing is a new theory in the field of signal processing in recent years. The theory points out that the signal can be observed at a rate lower than Nyquist sampling rate when the signal satisfies sparsity. It takes only a small number of data points to recover the signal accurately through the reconstruction algorithm, which makes it have a broad application prospect. The research of reconstruction algorithm is an important part of the theory of compression perception, and scholars at home and abroad have also carried out a lot of research, mainly focusing on three directions, one is convex optimization algorithm, the other is greedy algorithm. One is the combinatorial algorithm. The greedy algorithm has the advantages of low computational complexity, fast reconstruction speed and easy implementation, which makes it more suitable for practical application. On the basis of subspace pursuit (SP) algorithm with superior performance, this paper improves and optimizes the algorithm by taking into account the factors of performance, reconstruction time and realization area, etc. This paper designs and implements a reconstruction algorithm accelerator, optimizes the two least squares operation in SP algorithm into one least squares operation, reduces the computational complexity and area, and reduces the reconstruction time. At the same time, the reconstruction accuracy is guaranteed well. In the process of hardware implementation, the inverse matrix is adopted by ACD(Alternative Cholesky Decompositionalgorithm, and the algorithm is designed into a pulsating array structure. Therefore, the circuit performance is improved. For the complex cell divider realized by hardware, shift and subtraction are used instead, thus the critical path delay is eliminated. By multiplexing the multiplier unit in the ACD algorithm module to complete the multiplication operation in other modules, the realized area is further reduced. The reconstruction algorithm accelerator designed in this paper uses the observation signal of 64 length. By using Gao Si random distribution matrix, the digital signal with a signal length of 256 and a sparsity of 8 is reconstructed. The design is synthesized by SMIC 65nm process. The integrated area is 2316K Gatesand the working frequency is 222.2 MHz.
【学位授予单位】：复旦大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN911.7;TN47

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