10Gbps EPoC数字中频关键技术研究与实现

发布时间：2018-02-27 18:31

本文关键词： EPoC系统数字中频技术多相滤波并行DDS频率合成技术　出处：《电子科技大学》2014年硕士论文　论文类型：学位论文

【摘要】：作为我国网络设施建设发展的关键基础,加快发展电信网、广播电视网、互联网三网融合至关重要。三网融合中,为了满足支持多业务共存、家庭内部接入多终端、高带宽中强QoS等需求,EPoC技术作为下一代广播电视网的发展方向,实现了宽带化改造现有的光纤同轴混合网,来构建高速双向接入网。为满足EPoC系统的宽带高速传输需求,论文研究了10Gbps EPoC数字中频关键技术。论文中10Gbps EPoC数字中频设计,采用了多相滤波技术及并行DDS频率合成器技术,论文对这两种关键技术的设计、仿真与实现进行了仔细研究与分析。论文完成的主要工作如下:(1)论文结合数字中频的多相滤波技术研究,对适用于EPoC样机系统的数字中频的数字变频器进行算法设计和实现。总结出支持48MHz及192MHz两种信号带宽模式的数字变频器设计,设计仿真的浮点以及定点链路发送接收单边EVM均小于0.5%,并在FPGA上加以实现。论文对数字中频载波模块中的并行DDS频率合成器进行算法设计,仿真中DDS支持频段5MHz~1536MHz,且杂散大于60dB,并在FPGA上实现了该模块功能。(2)论文根据EPoC样机系统设计需求,总结出相关数据接口设计。在FPGA上实现了与基带板交互的数据接口,与ADC芯片、DAC芯片交互接口以及配置板内板间各个参数的SPI接口。与基带板交互数据接口达到了系统样机的10Gbps速率传输要求。(3)对数字中频射频前端系统进行了代码集成,搭建测试平台,对EPoC射频前端样机进行测试与分析。测试结果表明,各项指标均达到了EPoC射频前端样机的设计需求,样机发送和接收总体EVM指标小于1%,并且系统样机的频带利用率可达8.6bps/Hz。以上结论验证了论文设计的数字中频信号处理系统在EPoC射频前端样机中满足系统的高速率传输要求,为EPoC系统在我国的发展做出了贡献。
[Abstract]:As the key foundation of the construction and development of network facilities in China, it is very important to accelerate the development of telecommunication network, radio and television network and Internet triple network convergence. As the development direction of the next generation radio and television network, EPoC technology with high bandwidth, such as strong QoS and so on, realizes the broadband transformation of the existing optical fiber coaxial hybrid network to construct a high-speed two-way access network. In this paper, the key technology of 10Gbps EPoC digital intermediate frequency is studied. In this paper, the design of 10Gbps EPoC digital intermediate frequency is carried out, and the polyphase filter and parallel DDS frequency synthesizer are adopted. The two key technologies are designed in this paper. The main work of this paper is as follows: 1) the thesis combines with the polyphase filtering technology of digital intermediate frequency. The algorithm design and implementation of digital intermediate frequency converter suitable for EPoC prototype system are presented. The design of digital frequency converter which supports two signal bandwidth modes of 48MHz and 192MHz is summarized. In this paper, the floating-point and fixed-point link sending and receiving one-sided EVM are all less than 0.5 and implemented on FPGA. The parallel DDS frequency synthesizer in the digital if carrier module is designed in this paper. In the simulation, the DDS supports the frequency band of 5MHz / 1536MHz, and the stray is greater than 60dB, and realizes the function of the module on FPGA. (2) according to the design requirements of the EPoC prototype system, the paper summarizes the design of the related data interface, and realizes the data interface with the baseband board on the FPGA. The interface with the ADC chip and the SPI interface of the parameters between the inner board and the baseband board. The data interface with the baseband board meets the 10Gbps rate transmission requirement of the system prototype, and the code integration of the digital if RF front-end system is carried out. The test platform is built to test and analyze the EPoC RF front-end prototype. The test results show that all the indexes meet the design requirements of the EPoC RF front-end prototype. The overall EVM index of the prototype is less than 1, and the frequency band efficiency of the prototype can reach 8.6 BP / Hz. the above conclusion verifies that the digital if signal processing system designed in this paper can meet the requirement of high rate transmission in the EPoC RF front-end prototype. It has contributed to the development of EPoC system in our country.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN948.3

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