基于FPGA的通信信号信道化检测及其参数估计

发布时间：2018-02-28 08:22

本文关键词： 抗混叠数字信道化接收机参数测量 FPGA DDR3 RapidIO　出处：《南京理工大学》2014年硕士论文　论文类型：学位论文

【摘要】：近年来,随着无线电技术的迅猛发展,电子对抗的频带越来越宽,形式越来越复杂多变,传统的电子侦察接收机已经远远不能满足要求。于是,基于软件无线电构想的大动态范围、宽瞬时接收带宽、高灵敏度、高分辨率、多信号处理能力的数字信道化接收机应运而生。本文的主要研究内容有：分析了数字信道化的基本理论,针对信道化接收机相邻信道交界处有混叠的问题,推导了抗混叠信道化接收机结构,仿真试验和数据验证了该结构的可行性。研究了通信信号的检测和参数估计的问题。为了提高检测性能,提出了适应本工程的恒虚警检测方案。深入研究了通信信号测频算法,推导了基于测相的频率估计算法,并使用CORDIC算法优化结构,仿真试验表明,该算法能够达到课题的性能指标。探索了通信信号信道化检测及其参数估计的FPGA实现方法,详细分析了实现过程中遇到的问题并给出了解决方案。详细介绍了本工程中各模块的实现结构,为工程实验结果再现提供便利。实现了FPGA与DSP高速互连通信。一方面使用DDR3实现了高速率数据的存储和读取,研究了多种DDR3的控制方法,并对这些方法进行了比较和分析,提出了一些使用建议。另一方面使用RapidIO实现了FPGA与DSP高速数据传输,分析了IP核RapidIOv5.6的使用方法并在硬件上进行了实验,实验表明单路传输速率可以达到3.125Gbaud。
[Abstract]:In recent years, with the rapid development of radio technology, the frequency band of electronic countermeasure is becoming wider and wider, the form is more and more complex and changeable, the traditional electronic reconnaissance receiver is far from meeting the requirements. The digital channelized receiver based on the concept of software radio has the following characteristics: large dynamic range, wide instantaneous receiving bandwidth, high sensitivity, high resolution and multi-signal processing capability. The main contents of this paper are as follows:. The basic theory of digital channelization is analyzed and the structure of anti-aliasing channelized receiver is deduced aiming at the problem of aliasing at the junction of adjacent channels of channelized receiver. The feasibility of the structure is verified by simulation and data. The problem of communication signal detection and parameter estimation is studied. In order to improve the detection performance, a CFAR detection scheme adapted to this project is proposed. The frequency measurement algorithm of communication signal is studied in depth, and the frequency estimation algorithm based on phase measurement is derived. The CORDIC algorithm is used to optimize the structure and the simulation results show that the algorithm can achieve the performance index of the project. This paper explores the FPGA implementation method for channelization detection and parameter estimation of communication signals, analyzes the problems encountered in the process of implementation and gives the solutions. The implementation structure of each module in this project is introduced in detail. It is convenient to reproduce the results of engineering experiments. On the one hand, we use DDR3 to realize the storage and reading of high rate data, and study the control methods of various DDR3, and compare and analyze these methods. On the other hand, using RapidIO to realize high speed data transmission between FPGA and DSP, the use method of IP core RapidIOv5.6 is analyzed and the experiment on hardware is carried out. The experiment shows that the single transmission rate can reach 3.125 Gbaud.
【学位授予单位】：南京理工大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN911.23

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