60GHz射频前端集成技术分析与设计

发布时间：2018-03-04 03:31

本文选题：60GHz　切入点：毫米波　出处：《电子科技大学》2014年硕士论文　论文类型：学位论文

【摘要】：60GHz通信在前几年还是通信频段的一块空白,但随着这几年欧美日等国家相继推出专属于自己的60GHz通信频段,60GHz通信正式开放使用,逐渐开始蓬勃发展起来。随之英特尔、IBM等通信业巨头相继推出了应用于无线通信的芯片,由此带动了整个行业的发展。就目前态势来看,受限于功耗和成本的要求,60GHz通信技术还未完全成熟,离正式商用还有很长一段距离。在很长一段时间,射频前端芯片基本上都是用砷化镓(GaAs)材料制作,这主要是基于GaAs工艺截止频率高、噪声和增益比较理想方面的考虑,但随着无线通信的发展,对芯片的集成化和低功耗度提出了更高的要求。GaAs制作的芯片由于价格昂贵,已经无法满足大多数人的需求,而CMOS工艺以成本低、功耗低、易于集成、制备手段成熟等优点,令其成为近几年芯片业发展的主流。早期的CMOS工艺受限、截止频率低,但随着集成制作手段的提高,深亚微米级别的CMOS工艺越来越被人们所掌握,越来越多的芯片制造商把眼光投向了CMOS制作工艺上。本论文首先介绍了60GHz通信以及射频集成发展的概况,然后对通信系统射频前端的发射机和接收机结构进行了分析。然后介绍了片上集成的代表性产品--Vubiq公司研制的60GHz频段的通信开发系统。根据实际项目需要,考虑到成本和开发周期的问题,重点对混合集成方式构建的前端系统进行仿真。挑选合适的器件搭建了60GHz的发射、接收通信系统链路,主要对搭建系统进行增益、选择性、相位噪声、噪声系数、路径衰减等方面的仿真和结果分析。本文后半段对60GHz低噪声放大器射频芯片(RFIC)进行分析与设计:首先根据指标要求,分析了用于60GHz频段的低噪声放大器的拓扑结构,从增益、噪声系数、功耗三方面确定设计方案,接着用Cadence IC 5141集成电路设计软件,分别在台积电(TSMC)0.18μm和0.13μm RF CMOS工艺下,对不同的输入匹配结构进行仿真设计,最终在0.13μmRF CMOS工艺下设计出了一款工作在60GHz频段、噪声系数小于10dB、增益大于12dB、功耗小于100mW的低噪声放大器。
[Abstract]:The 60GHz communication is still a blank in the communication frequency band in the past few years. However, with the introduction of 60GHz communication band which belongs to Europe, America and Japan and other countries in the past few years, the 60GHz communication band has been officially opened for use. Gradually began to flourish. With the Intel, IBM and other communications giants have introduced chips for wireless communications, which has led to the development of the entire industry. From the current situation, Limited by power consumption and cost requirements, 60GHz communication technology is not yet fully developed, and it is still a long way from commercial use. For a long time, RF front-end chips are basically made of GaAs (GaAs) materials. This is mainly based on the consideration of high cut-off frequency, noise and gain of GaAs process. However, with the development of wireless communication, the chip made by .GaAs is more expensive because of the higher requirement of chip integration and low power consumption. CMOS process has become the mainstream of chip industry development in recent years because of its advantages of low cost, low power consumption, easy integration, mature preparation methods, etc. The early CMOS process is limited, and the cut-off frequency is low. However, with the improvement of integrated manufacturing methods, the deep submicron CMOS process has been more and more mastered by people. More and more chip manufacturers are focusing on CMOS fabrication technology. This paper first introduces the development of 60GHz communication and RF integration. Then, the transmitter and receiver structure of RF front-end of communication system are analyzed. Then, the representative product of on-chip integration is introduced, which is a 60GHz communication development system developed by Vubiq Company. Considering the cost and the development cycle, the simulation of the front-end system constructed by the hybrid integration mode is emphasized. The appropriate device is selected to build the 60GHz transmission and receive communication system link, and the gain and selectivity of the built system are mainly carried out. Simulation and result analysis of phase noise, noise coefficient, path attenuation and so on. In the second half of this paper, the RF chip RFICs of 60GHz LNA are analyzed and designed. The topology of the low noise amplifier used in the 60GHz band is analyzed. The design scheme is determined from three aspects: gain, noise coefficient and power consumption. Then, the Cadence IC5141 integrated circuit design software is used in the TSMC 0.18 渭 m and 0.13 渭 m RF CMOS technology, respectively. Different input matching structures are simulated and designed. Finally, a low noise amplifier operating at 60GHz frequency band with noise coefficient less than 10 dB, gain greater than 12 dB and power consumption less than 100MW is designed under 0.13 渭 mRF CMOS process.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN928;TN722.3

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