TPC串行和并行迭代译码器的研究和实现

发布时间：2018-03-05 06:05

本文选题：无线通信　切入点：信道编码　出处：《西安电子科技大学》2014年硕士论文　论文类型：学位论文

【摘要】：近年来,无线通信技术得到了迅猛发展。无线通信的信道同有线通信相比,存在更多的干扰和更强的衰落,这无疑降低了无线通信的可靠性。为了提高无线通信系统的可靠性,降低误码率,通常采用信道编码技术。信道编码技术已经成为无线通信中十分重要的一部分。Turbo乘积码是一种新型、高效的信道编码技术,其采用线性分组码作为子码,译码过程采用软输入软输出的译码算法,使得其译码过程相对Turbo码要简单许多,而译码性能上又十分可靠。本文首先介绍了信道编码的发展历史,和TPC编译码的基本原理,着重介绍了基于ChaseII译码算法的软输入软输出迭代译码原理。接下来分析了影响TPC译码性能的一些因素,并在Matlab软件环境下进行了仿真,这些因素将决定设计译码器时的参数选取。然后分析了ChaseII译码算法的简化方法,这些简化条件将使译码器的复杂度降低。然后,设计了串行和并行两种迭代方式的译码器,并且根据性能仿真结果比较了二者的性能差异。最后,使用Verilog语言完成了TPC编译码器的FPGA实现。其中编码器较为简单,串行和并行迭代译码器较为复杂。在QuartusII环境下完成编译码器的设计,着重比较了两种不同迭代方式译码器的译码延时和资源占用情况。使用ModelSim软件观察译码输出波形图,并将译码输出结果与发送的原始比特进行对照,验证译码器的正确性。
[Abstract]:In recent years, wireless communication technology has developed rapidly. Compared with wired communication, the channel of wireless communication has more interference and stronger fading, which undoubtedly reduces the reliability of wireless communication. To reduce the bit error rate (BER), channel coding technology is usually adopted, which has become a very important part of wireless communication. Turbo product code is a new and efficient channel coding technique, which uses linear block codes as subcodes. The decoding process adopts soft input and soft output decoding algorithm, which makes the decoding process much simpler than Turbo code, and the decoding performance is very reliable. Firstly, this paper introduces the history of channel coding and the basic principle of TPC coding and decoding. The principle of soft input and soft output iterative decoding based on ChaseII decoding algorithm is introduced emphatically. Then, some factors that affect the decoding performance of TPC are analyzed, and the simulation is carried out under the environment of Matlab software. These factors will determine the selection of parameters when designing the decoder. Then, the simplified method of ChaseII decoding algorithm is analyzed, which will reduce the complexity of the decoder. Then, the serial and parallel iterative decoders are designed. Finally, the FPGA implementation of TPC codec is implemented with Verilog language. The encoder is relatively simple. The serial and parallel iterative decoders are more complicated. The decoder is designed in QuartusII environment, and the decoding delay and resource occupation of two different iterative decoders are compared. The output waveform diagram of decoding is observed by ModelSim software. The output of the decoder is compared with the original bit to verify the correctness of the decoder.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN915.04;TN914

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