基于FPGA的雷达运动目标检测系统设计

发布时间：2018-03-07 13:16

本文选题：现场可编程逻辑门阵列　切入点：动目标显示　出处：《西安电子科技大学》2014年硕士论文　论文类型：学位论文

【摘要】：雷达工作的电磁环境比较复杂,经常受到各种杂波干扰。为了提取出所需目标,需要对杂波进行抑制。在工程实现中,一般采用动目标显示、动目标检测、恒虚警和杂波图等方法来实现。现场可编程逻辑门阵列(FPGA)处理速率高,带宽大,配合DDR3强大的缓存能力,可以实现对雷达回波数据的高速处理。本论文对运动目标检测的相关算法进行了仿真分析,给出了工程实现方式,论文主要从以下几点展开的:1.从锯齿线性调频连续波雷达的工作原理出发,仿真了抑制固定地物杂波的动目标显示技术。比较了动目标显示的不同实现方式和优缺点;针对动目标检测技术,给出两种多普勒滤波器组的实现方式;针对雷达信号检测时的恒虚警检测处理,给出了四种恒虚警电路的实现方式;利用零通道幅度信息,建立了零速杂波图,并给出了超杂波检测方法;针对多普勒聚心技术,给出了工程实现方式。2.完成了硬件平台的设计。给出了信号处理板的结构框图,该处理板板间和板内数据传输带宽大,可以满足内外接口需求。给出了该硬件平台的FPGA资源,该FPGA集成度高,功耗低,并且能够反复编程;内部流水处理,能够大大降低处理延时,提高数据处理速度;有着更多的逻辑资源、乘法器和控制器等硬件资源,可以快速的进行信号处理和逻辑控制。FPGA内部存储空间有限,在进行数据处理的过程中需要缓存大量的数据。DDR3由于具有高速、大容量存储等优点,可以很好的与FPGA配合来实现数据缓存的功能。3.给出了雷达信号处理的运动目标检测方案。设计了动目标显示、动目标检测、恒虚警、超杂波检测和多普勒聚心等功能的框图。在数据缓存控制时,加入数据重排的功能。通过对DDR3地址位的控制,配合FPGA内部的缓存RAM,可以根据后级处理的需求,实现数据的重排,极大的缩短了信号处理时间。4.给出实测数据的处理结果,验证了FPGA所实现功能的正确性。并对本文中存在的一些问题进行总结,给出了一些改进性措施。
[Abstract]:The electromagnetic environment of radar work is complex, and it is often disturbed by various clutter. In order to extract the desired target, it is necessary to suppress the clutter. In engineering implementation, moving target display is generally used to detect moving target. Field Programmable Logic Gate Array (FPGA) has high processing speed, large bandwidth and strong buffer capacity with DDR3. The high speed processing of radar echo data can be realized. In this paper, the related algorithms of moving target detection are simulated and analyzed, and the engineering realization method is given. This paper mainly focuses on the following points: 1. Based on the working principle of serrated LFM continuous wave radar, this paper simulates the display technology of moving target for suppressing clutter of fixed ground object, and compares the different realization methods, advantages and disadvantages of moving target display; Aiming at moving target detection technology, two kinds of Doppler filter banks are given, four kinds of CFAR circuits are given for radar signal detection and processing, and zero channel amplitude information is used. The zero-velocity clutter diagram is established, and the detection method of super-clutter is given, and the engineering realization mode .2. the design of hardware platform and the structure block diagram of the signal processing board are given, according to the Doppler centroid technology, the design of the hardware platform is completed, and the structure of the signal processing board is given. The FPGA resource of the hardware platform is given, which has the advantages of high integration, low power consumption, and can be programmed repeatedly. Can greatly reduce processing delay, improve data processing speed, with more logical resources, multiplier and controller and other hardware resources, can quickly carry out signal processing and logic control. FPGA internal storage space is limited. In the process of data processing, it is necessary to cache a large amount of data. DDR3 has the advantages of high speed, large capacity storage, etc. It can work well with FPGA to realize the function of data cache. 3. The scheme of moving target detection for radar signal processing is given. The moving target display, moving target detection, constant false alarm rate are designed. In the data cache control, the function of data rearrangement is added. Through the control of DDR3 address bit and the buffer within FPGA, the data rearrangement can be realized according to the demand of post-processing. The signal processing time is greatly shortened. 4. The processing results of the measured data are given, and the correctness of the functions realized by FPGA is verified. Some problems in this paper are summarized, and some improvement measures are given.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN957.51

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