微型SAR数据回放技术研究

发布时间：2018-03-12 22:44

本文选题：微型SAR　切入点：数据回放　出处：《国防科学技术大学》2014年硕士论文　论文类型：学位论文

【摘要】：在SAR实时信号处理机的研制调试过程中,数据回放技术至关重要。本文以微型SAR实时成像处理机的研制为背景,基于实时处理机平台,展开了大数据量高速数据回放技术的研究并获得了实际应用。该回放技术的实现以大容量CF卡作为存储介质,以FPGA作为主控芯片,通过串行RapidIO技术实现了高速数据传输,满足了实时成像处理机对数据回放的要求。本文主要工作概括如下:1、研究了CF卡的技术标准及其FAT32文件管理系统。为降低文件管理系统的操作复杂度和提高CF卡的数据传输速率,通过对CF卡中文件的定量操作以及FAT表、FDT表和文件数据区的分开管理,设计了实时文件管理系统并分析了其性能。所设计的实时文件管理系统具有操作简单可靠的特点。2、研究了RapidIO技术并给出了串行RapidIO(SRIO)在Xilinx Virtex6系列FPGA和TMS320C6678 DSP中的实现方法。为满足数据回放过程中的数据传输需求,设计了FPGA与DSP之间的SRIO链路,通过具体配置FPGA中SRIO IP核和修改其中HDL源码以及初始化DSP中SRIO模块,实现了FPGA与DSP间的数据传输,具有数据传输速率快的特点。3、介绍了某微型SAR实时成像处理机,通过处理机实际工作过程中数据流程的分析,设计了一种定时突发的数据回放方案,实现了对实时成像处理机机载飞行条件下工作过程的模拟。在详细研究了数据回放技术的实现途径的基础上,实现了SAR数据的回放,并利用CCS5和ChipScope软件对回放数据的正确性进行了验证。通过对突发过程中数据回放速率的测试,数据传输速率稳定在70.6MB/s,满足高速数据回放的要求。4、为满足实时成像处理机调试的需求,设计实现了控制数据回放的上位机软件,进行了功能的正确性测试。测试结果表明该上位机可灵活有效地实现数据回放过程的控制。最后,结合上位机的控制给出了数据回放在实时成像处理机调试过程中的应用。
[Abstract]:In the process of development and debugging of SAR real time signal processor, data playback technology is very important. This paper takes the development of micro SAR real time imaging processor as the background, based on the real time processor platform. In this paper, the high speed data playback technology of large amount of data is studied and applied in practice. The realization of this technology is based on large capacity CF card as storage medium, FPGA as main control chip and serial RapidIO technology to realize high speed data transmission. The main work of this paper is summarized as follows: 1. The technical standard of CF card and its FAT32 file management system are studied. In order to reduce the operational complexity of the file management system and improve the CF card. Data transfer rate, Through the quantitative operation of the files in the CF card and the separate management of the FAT table and the file data area, The real-time file management system is designed and its performance is analyzed. The designed real-time file management system has the characteristics of simple and reliable operation. The RapidIO technology is studied and the implementation of serial rapid file management system in Xilinx Virtex6 series FPGA and TMS320C6678 DSP is given. In order to meet the requirements of data transmission in the process of data playback, The SRIO link between FPGA and DSP is designed. By configuring the SRIO IP core in FPGA, modifying the source code of HDL and initializing the SRIO module in DSP, the data transmission between FPGA and DSP is realized. In this paper, a micro SAR real-time imaging processor is introduced. Through the analysis of the data flow in the actual working process of the processor, a timing burst data playback scheme is designed. The simulation of the working process of real-time imaging processor under airborne flight condition is realized. Based on the detailed study of the implementation of data playback technology, the playback of SAR data is realized. The correctness of playback data is verified by using CCS5 and ChipScope software. The data transmission rate is stable at 70.6 MB / s, which meets the requirement of high speed data playback. In order to meet the needs of the debugging of real-time imaging processor, a host computer software is designed and implemented to control the data playback. The test results show that the upper computer can control the data playback process flexibly and effectively. Finally, the application of data playback in the debugging process of real-time imaging processor is given in combination with the control of the upper computer.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN957.52

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