宽频率范围低抖动锁相环设计

发布时间：2018-03-16 17:22

  本文选题：锁相环　切入点：宽输入输出频率范围　出处：《国防科学技术大学》2014年硕士论文　论文类型：学位论文

【摘要】：随着集成电路飞速发展,电子产品日新月异的更新给集成电路的设计提出了高速换代的要求。而模拟集成电路设计要遵循各性能参数相互制约的关系,这使的某一个性能参数非常好的时候,另一个性能参数却可能成为短板,所以同时适用于不同性能指标的模拟电路设计具有很大挑战性。锁相环作为模拟电路设计的一个典型代表,其在固定输入输出频率时的低抖动要求较容易实现,但是当输入或输出频率变化时,势必会使某些固定的环路参数成为一个变化的量,使PLL系统成为一个动态系统,该系统对不同频率输出点的抖动性能没有一个很好的收敛性,所以宽输入输出频率范围的低抖动锁相环设计是一个难点。本文在40nm CMOS工艺下研究了宽输入输出频率范围锁相环的低抖动实现,通过系统级,行为级、电路级和版图级的全方位研究,得到影响锁相环输出抖动的三个主要因素:电源噪声、压控振荡器控制电压波动和抖动在整个输出频率范围的不一致性。为了实现抖动在整个输出频率范围的一致性,本文改进了常规的自适应带宽锁相环架构,通过理论推导,验证了该架构带宽和阻尼因子随参考频率的的变化可以自适应。为了Vc电压波动的抑制,本文从锁相环行为级分析了鉴频鉴相器和电荷泵的非理想因素,在此基础上改进了鉴频鉴相器和电荷泵的电路结构。验证结果表明锁相环在锁定状态下,本文采用的设计使压控振荡器控制信号上的峰峰值从2.1mV下降到0.13mV,下降了一个多数量级。为了抑制电源噪声对锁相环输出抖动的影响,本文从锁相环外部设计了低压差稳压器,实现弱噪声电源供电;然后对压控振荡器等模块进行了高电源抑制比的设计。验证结果表明本文的设计策略使电源上10%的噪声被衰减到不足0.5%。本文最后实现了一款40nm工艺下的宽输入输出频率范围低抖动锁相环,并设计了版图和测试芯片。通过电路与版图的仿真结果和文献中的PLL仿真结果对比,本文所设计的PLL抖动非常低,10000个周期的周期周期峰峰值抖动只有不到1%,RMS抖动也只有1.2‰,超过了文献中同类型的PLL。并且该PLL的抖动一致性较好,实现了宽输入输出频率范围高性能PLL的要求。
[Abstract]:With the rapid development of integrated circuits, the rapid updating of electronic products has put forward the requirement of high-speed replacement for the design of integrated circuits. This makes one of the performance parameters very good, while the other performance parameter can become a short plate, Therefore, it is very challenging to design analog circuits with different performance indexes. As a typical example of analog circuit design, the low jitter requirement of PLL in fixed input and output frequency is easy to realize. However, when the input or output frequency changes, some fixed loop parameters will become a variable, and the PLL system will become a dynamic system. The system does not have a good convergence to the jitter performance of different frequency output points. Therefore, the design of low jitter PLL with wide input and output frequency range is a difficulty. In this paper, the low jitter realization of PLL with wide input and output frequency range is studied in 40nm CMOS process, which is implemented at system level and behavior level. By studying the circuit level and layout level, three main factors affecting the output jitter of the PLL are obtained: power noise, Voltage controlled oscillator controls the inconsistency of voltage fluctuation and jitter in the whole output frequency range. In order to realize the consistency of jitter in the whole output frequency range, the conventional adaptive bandwidth PLL architecture is improved in this paper. It is verified that the variation of bandwidth and damping factor with reference frequency is adaptive. In order to suppress the voltage fluctuation of VC, the non-ideal factors of phase discriminator and charge pump are analyzed from the behavior level of phase-locked loop. The circuit structure of the phase discriminator and the charge pump is improved. The results show that the PLL is in the locked state. The design adopted in this paper reduces the peak and peak value of the VCO control signal from 2.1 MV to 0.13 MV, which is a multi-order of magnitude decrease. In order to suppress the influence of power noise on the output jitter of PLL, a low-voltage differential regulator is designed from the outside of PLL. Realize the power supply of weak noise power supply; Then the VCO and other modules are designed with high PSRR. The verification results show that the design strategy of this paper makes the noise of 10% in the power supply attenuated to less than 0.5. Finally, a 40nm wide input transmission is realized in this paper. Out of frequency range low jitter PLL, The layout and test chip are designed. Compared with the simulation results of the circuit and layout and the PLL simulation results in the literature, the PLL jitter designed in this paper is very low. The jitter consistency of the PLL is better than that of the same type of PLLs in the literature, and the requirement of high performance PLL with wide input and output frequency range is achieved.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN911.8
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本文编号：1620893