非结构化LDPC码的FPGA设计与实现

发布时间：2018-03-18 18:15

本文选题：非结构化　切入点：映射方法　出处：《西安电子科技大学》2014年硕士论文　论文类型：学位论文

【摘要】：低密度奇偶校验(Low-Density Parity-Check,LDPC)码具有优异的性能,且译码涉及的数据运算简单,该类码字的FPGA实现已经广泛应用于数字电视和通信等领域。非结构化LDPC码检验矩阵中非零元素的分布没有任何规律,因而比结构化LDPC码的性能较好。但是,由于非结构化码字的校验矩阵没有循环结构或者准循环结构,增加了非结构码字在逻辑设计与实现中的复杂度,同时矩阵中“1”不规律的分布增加了FPGA实现的逻辑设计难度。因此,本文重点研究了非结构化码字的逻辑设计与实现,并提出一种基于行列置换的映射方法,以降低不规律度分布的影响,减少对码字译码性能的影响,能够有效地降低实现复杂度。本文的主要内容如下:首先,介绍了两种不同结构的LDPC码,详细推导了几种性能较好的译码算法,并针对同一组码字给出了使用不同算法时的性能比较结果。然后,比较了不同结构的码字在逻辑设计与实现中的优缺点,并且提出了一种基于行列置换的映射方法,以简化非结构化LDPC译码器的逻辑设计,有效降低FPGA实现的难度,还具体地分析了量化方案和译码算法中几个关键参数对码字性能的影响。最后,根据本文提出的用于简化逻辑的映射方法,基于串行结构设计并完成了非结构化(548,274)LDPC译码器的逻辑设计,并进行综合仿真和布局布线,可以较准确地译出码字。针对非结构化LDPC译码器的FPGA设计与实现,本文提出了一种并行设计思路以解决定点数寻址的冲突问题,从而获得较高的数据处理速率。经实际下板验证,非结构化(548,274)LDPC译码器可以正常工作,最高工作频率为213.549MHz,经计算数据吞吐率可达20Mbps左右。
[Abstract]:Low-Density Parity-Check-based LDPC (LDPC) codes with low density parity check have excellent performance, and the data operation involved in decoding is simple. The FPGA implementation of this kind of codewords has been widely used in digital television and communication fields. The distribution of nonzero elements in the unstructured LDPC code verification matrix has no rules, so it is better than the structured LDPC code. However, the performance of the unstructured LDPC code is better than that of the structured LDPC code. Because the check matrix of unstructured codewords has no cyclic structure or quasi-cyclic structure, the complexity of unstructured codewords in logic design and implementation is increased. At the same time, the irregular distribution of "1" in the matrix makes the logical design of FPGA more difficult. Therefore, this paper focuses on the logical design and implementation of unstructured codewords, and puts forward a mapping method based on column and column permutation. In order to reduce the influence of irregular degree distribution and the influence on codeword decoding performance, the implementation complexity can be reduced effectively. The main contents of this paper are as follows: firstly, two kinds of LDPC codes with different structures are introduced. Several decoding algorithms with good performance are deduced in detail, and the performance comparison results of different algorithms are given for the same group of codewords. Then, the advantages and disadvantages of different structure codewords in logic design and implementation are compared. A mapping method based on column and column permutation is proposed to simplify the logic design of unstructured LDPC decoder and reduce the difficulty of FPGA implementation. The effects of several key parameters in quantization scheme and decoding algorithm on codeword performance are also analyzed in detail. Finally, according to the mapping method proposed in this paper for simplifying logic, Based on the serial structure, the logic design of the unstructured LDPC decoder is designed and completed, and the integrated simulation and layout routing are carried out. The codewords can be translated more accurately. The FPGA design and implementation of the unstructured LDPC decoder is presented. In this paper, a parallel design method is proposed to solve the problem of addressing the fixed point number, so as to obtain a higher data processing rate. The unstructured LDPC decoder can work normally, which is verified by the actual downboard. The highest operating frequency is 213.549 MHz, and the calculated data throughput is about 20Mbps.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN911.22;TN791

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