基于高速串行交换的通用信号处理机设计

发布时间：2018-03-20 06:10

本文选题：高速串行　切入点：交换　出处：《西安电子科技大学》2014年硕士论文　论文类型：学位论文

【摘要】：当前,数字信号处理算法日趋复杂,大数据量及高计算复杂度对信号处理机提出了更大的挑战。根据大规模计算要求,信号处理机一般集成众多处理节点来实现并行处理。当处理节点增多到一定数量时,点对点的互连方式将大大限制数据的传输带宽,进而影响信号处理机的整体性能。因此,研究基于高速串行交换的可扩展信号处理机,使系统中任意节点间享有独立的高传输带宽,具有非常重要的现实意义。本文设计了一种基于高速串行交换的FPGA+多核DSP通用信号处理机,具体内容如下:(1)给出了信号处理机的整体设计方案。在开发验证的基础上,选用性能强劲的FPGA和DSP作为处理节点。同时,采用最新的SRIO和PCIe交换芯片,实现信号处理机各处理节点之间的互连。(2)详细分析了各处理节点的功耗需求(电压值、电压类型及电流值)和时钟需求(时钟频率和电平逻辑),并依据需求制定了相应的电源和时钟设计方案;随后介绍了数据交换模块的设计原理和思路,并阐述了各接口的互连方式,重点确定了各处理节点和交换芯片的配置方式;最后分析了高速信号传输时需要注意的电源完整性和信号完整性问题,并设定了多层PCB板的叠层结构。(3)重点描述了各交换芯片的寄存器配置流程,并依据各高速串行协议及其数据包格式进行FPGA和DSP端驱动程序的开发,编写了各处理节点通过交换芯片进行数据传输的测试程序,达到了各处理节点中数据灵活交互的目的。论文虽然实现了数据的灵活传输,但传输速率与理论值之间还有一定差距,需要进一步优化。除此之外,本方案只使用了交换芯片最基本的功能,一些复杂但更有应用前景的特性尚待开发。
[Abstract]:At present, the digital signal processing algorithm is becoming more and more complex. The large amount of data and high computational complexity pose a greater challenge to the signal processor. Signal processors generally integrate many processing nodes to achieve parallel processing. When processing nodes increase to a certain number, point-to-point interconnection will greatly limit the transmission bandwidth of data, thereby affecting the overall performance of the signal processor. This paper studies an extensible signal processor based on high speed serial switching, which can make any node in the system enjoy independent high transmission bandwidth. This paper designs a FPGA multi-core DSP universal signal processor based on high speed serial switching. The main contents are as follows: 1) the whole design scheme of the signal processor is given. The powerful FPGA and DSP are selected as processing nodes. At the same time, using the latest SRIO and PCIe switching chips, the power requirement (voltage value) of each processing node is analyzed in detail. Voltage types and current values) and clock requirements (clock frequency and level logic), and according to the requirements of the corresponding power supply and clock design, then introduced the data exchange module design principles and ideas, The interconnection mode of each interface is expounded, and the configuration mode of each processing node and switch chip is determined. Finally, the problems of power supply integrity and signal integrity that should be paid attention to in high-speed signal transmission are analyzed. The stack structure of multilayer PCB board is set up. The register configuration flow of each switch chip is described emphatically, and the driver of FPGA and DSP is developed according to each high speed serial protocol and its data packet format. The test program of data transmission between each processing node through the switch chip is written, which achieves the purpose of flexible data exchange in each processing node. Although the paper realizes the flexible transmission of data, However, there is still a gap between the transmission rate and the theoretical value, which needs further optimization. In addition, this scheme only uses the most basic functions of the switching chip, and some complex but more promising characteristics need to be developed.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN911.7

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