取样示波器数字信号处理模块设计与实现

发布时间：2018-03-23 02:16

本文选题：取样示波器　切入点：数字信号处理模块　出处：《电子科技大学》2014年硕士论文　论文类型：学位论文

【摘要】：取样示波器具有高带宽和高采样率,能够测量高速快变电子信号。取样示波器的数字信号处理模块是取样示波器必不可少的部分。本论文阐述了取样示波器的基本框架,并结合本项目的取样示波器仪器来阐述本论文的取样示波器的数字信号处理模块的设计方案及其实现。该数字信号处理模块的工作内容从总体上可以分为数字信号处理模块的硬件的设计与实现和其软件的设计与实现,从具体的实现内容可以分为:与上位机通信、控制底层FPGA采集系统、接受并处理来自采集系统的原始数据、bootloader。硬件设计的内容包括:建立最小系统、采用网络与上位机PC来建立通讯,与底层FPGA通过外部存储器接口和GPIO等接口建立通信。本设计的硬件选取以TI公司的TMS320C6747为核心的数字信号处理平台。由于该平台具有丰富的接口,如:网络接口、外部存储器接口、USB、UART、SPI等,所以该平台能实现设计要求。硬件的实现流程是:硬件设计方案确定后,投版,然后对新电路板的调试。调试内容分为单板调试与联机调试。单板调试的内容有:与本设计相关的网络、中断、启动等模块功能的调试,以及与上位机的脱机调试。联机调试的内容有:与底层FPGA之间的握手与通信,控制仪器的采集系统等内容。最终的硬件测试结果是硬件各个模块均能正常工作,并且实现联机的所有测量内容。本设计的软件的操作系统采用DSP/BIOS内核,并采用网络开发套件(NDK)来设计网络通信,进而设计一套多线程并发执行的软件程序。该多线程是一个父线程,两个子线程。父线程作为网络服务器端的守护线程,并一直存在直至系统关闭。两个子线程可以解析上位机网络命令,与底层FPGA通信,并通过这两个子线程完成并发执行。另外软件设计包括bootloader内容。由于高速取样示波器的时基误差导致测量结果不完善,所以本文对时基误差做了概述。时基误差包括时基抖动和时基失真。本设计采用总计平均的方法对随机噪声做了处理,采用正弦拟合的方法对时基失真做估算。经过调试,本设计的性能满足设计需求。本设计实现了取样示波器数字信号处理模块的基本功能,并估算了仪器的时基失真。
[Abstract]:Sampling oscilloscope has high bandwidth and high sampling rate, it can measure high speed and fast changing electronic signal. The digital signal processing module of sampling oscilloscope is an essential part of sampling oscilloscope. This paper describes the basic frame of sampling oscilloscope. The design and implementation of the digital signal processing module of the sampling oscilloscope in this paper are described. The working content of the digital signal processing module can be divided into digital signal processing module in general. The design and implementation of the hardware and software of the processing module, From the concrete implementation content can be divided into: communication with the host computer, control the bottom FPGA acquisition system, receive and process the raw data from the acquisition system bootloader.hardware design content includes: build the minimum system, Using network and PC to establish communication, The hardware of this design is a digital signal processing platform with TI's TMS320C6747 as the core. Because of its rich interface, such as network interface, the hardware of this platform is designed to communicate with the underlying FPGA through external memory interface and GPIO interface. The external memory interface is USBU UART SPI and so on, so the platform can meet the design requirements. Then the debugging of the new circuit board is divided into single board debugging and on-line debugging. The contents of on-line debugging include handshake and communication with bottom FPGA, acquisition system of control instrument and so on. The final hardware test result is that each module of hardware can work normally. The operating system of the software is designed with DSP/BIOS kernel and network development kit (NDK) to design network communication. The multithread is a parent thread, two child threads. The parent thread is the daemon thread on the network server side. Two sub-threads can parse the host computer network commands and communicate with the underlying FPGA. In addition, the software design includes bootloader content. Because of the time-base error of high-speed sampling oscilloscope, the measurement result is not perfect. Therefore, the time base error is summarized in this paper. The time base error includes time base jitter and time base distortion. In this design, the random noise is treated by the method of total average, and the time base distortion is estimated by the method of sinusoidal fitting. The function of the digital signal processing module of the sampling oscilloscope is realized, and the time-base distortion of the instrument is estimated.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN911.72;TM935.3

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