高速Turbo乘积码编译码算法及其FPGA实现

发布时间：2018-03-23 17:12

本文选题：Turbo乘积码　切入点：并行译码器　出处：《西安电子科技大学》2014年硕士论文

【摘要】：Turbo乘积码(TPC)自1994年提出后,其优异的性能引起了研究人员的广泛关注。作为一种高效的前向差错控制(FEC)信道编码技术,TPC在码率、译码性能和硬件复杂度方面具有很大的优势,具有不错的应用前景。随着通信技术的迅猛发展,人们对数据传输速率的要求越来越高。传统的串行TPC译码器占用资源较少,但是译码延时太大,很难满足高速的要求,人们纷纷把目光转向并行译码器。TPC的码字特点使其很容易提高并行度,但是单纯的行列并行译码需要使用大量的存储资源,且控制比较复杂。本文中我们提出了一种新的并行译码器,大大提高了TPC译码器的吞吐量。在实现中使用了多种实现高速的设计方法:采用新的译码器结构减少行列译码之间的时延;设计了一种每个时钟可以处理一行码字的分量码译码器;分量码译码器找最不可靠位时采用快速排序减少时延;比较候选码字相关度量确定最优码字和竞争码字时采用快速排序减少时延等。这些技术可以显著提高译码器的吞吐量。本文结合中国电子科技集团公司第十研究所的合作课题,采用VHDL作为开发语言,在Xilinx Virtex-5系列的xc5vlx330芯片上实现了三种不同码率的TPC编译码器:(32,26,4)?(32,26,4)TPC、(64,57,4)?(32,26,4)TPC和(64,57,4)?(64,57,4)TPC,并且把它们合成一个码率兼容的编译码器,通过一个mode信号的不同输入进行不同的码字选择。译码器总资源只是略高于占用资源最多的单个编译码器,实现了资源的最优化。经测试,三种TPC的吞吐量分别为315Mbps、502Mbps和1083Mbps,实现了Gbps量级吞吐量的译码器。
[Abstract]:Turbo Product Code (Turbo) has attracted wide attention since it was proposed in 1994. As an efficient forward error control (FEC) channel coding technique, it has great advantages in bit rate, decoding performance and hardware complexity. With the rapid development of communication technology, the demand for data transmission rate is becoming higher and higher. The traditional serial TPC decoder takes less resources, but the decoding delay is too long, so it is difficult to meet the requirements of high speed. People turn their attention to the character of parallel decoder. TPC makes it easy to improve the parallelism, but the simple parallel decoding of column and column requires a lot of storage resources. In this paper, we propose a new parallel decoder. The throughput of the TPC decoder is greatly improved. A variety of high-speed design methods are used in the implementation: a new decoder structure is used to reduce the delay between the rows and rows; A component code decoder which can process a line of codewords per clock is designed, and the fast sorting is used to reduce the delay when the component decoder finds the least reliable bit. Comparing candidate codeword correlation metrics to determine optimal codewords and competing codewords, fast sorting is used to reduce delay and so on. These techniques can significantly improve the throughput of the decoder. Using VHDL as the development language, three kinds of TPC codecs with different bit rates are implemented on xc5vlx330 chips of Xilinx Virtex-5 series. TPCU 64N 57U 4U???!!! 32!!! 26!!! 4!!! 4!!! 4? TPC and 64TPC? The total resource of the decoder is only slightly higher than that of the single decoder, which occupies the most resources, and synthesizes them into a bit-rate compatible codec and selects different codewords through different inputs of a mode signal, and the total resource of the decoder is only slightly higher than that of a single codec with the largest amount of resources. The test results show that the throughput of the three kinds of TPC is 315Mbps502Mbps and 1083Mbpss respectively, and the decoder of Gbps throughput is realized.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN911.22;TN791

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