基于FPGA的GNSS信号载波同步技术研究

发布时间：2018-04-01 22:28

本文选题：GNSS　切入点：载波同步　出处：《大连海事大学》2015年硕士论文

【摘要】：最近几年里,在卫星通信、卫星定位以及遥测遥控等技术的快速发展过程中,载波跟踪这门技术也越来越受到广大研究人员的青睐,并且有了突破性的进展。在做国家支撑计划课题“AIS/GNSS船载导航设备关键技术与系统研制(2012BAH36B02)"时,需要设计一种通用型锁相环,用于设备接收端进行载波提取。对于载波受到抑制的双边带调制方式,需要采用直接提取法来获得载波。直接提取法有两种,平方环载波提取法和同相正交环(即科斯塔斯环)载波提取法。平方环载波提取法的一个很大限制是,整个环路要工作在载波的二倍频上当载波频率很高时,该方法的性价比比较低,因此,本文主要研究科斯塔斯环载波提取法。科斯塔斯环作为锁相环的一项应用,在实际载波同步中发挥着很大的作用,本文首先针对锁相环技术进行了深入的研究,主要包括锁相环的结构组成、工作原理和基本性能。然后具体研究了科斯塔斯环的实现方法,对其进行了结构划分,在大结构上主要分为三个模块,分别是鉴相器模块、环路滤波模块和DDS模块(这也是锁相环的三个主要组成部分),其中在鉴相器的实现上又分了两个子模块,相乘器子模块和FIR低通滤波器子模块。在明确了模块划分之后,对每一个小模块进行了设计与实现。本文主要在Xilinx公司研发的ISE硬件开发平台上,采用Verilog HDL硬件描述语言进行编程实现,仿真软件是Modelsim SE 6.5,在各个模块功能仿真都达到预期目标的条件下,开始顶层模块的仿真,最后使用Virtex4开发板对整个程序进行了板上验证,并将最终的验证结果在示波器上显示出来。
[Abstract]:In recent years, with the rapid development of satellite communication, satellite positioning and telemetry and remote control technology, carrier tracking technology has been more and more favored by the majority of researchers, and has made a breakthrough.In the course of national support project "key technology and system development of AIS/GNSS shipborne navigation equipment", it is necessary to design a general phase-locked loop for carrier extraction at the receiving end of the equipment.For the two-sided band modulation with suppressed carrier, direct extraction is needed to obtain the carrier.There are two kinds of direct extraction methods: square loop carrier extraction method and in phase orthogonal loop (Kostas loop) carrier extraction method.A great limitation of the square loop carrier extraction method is that when the carrier frequency is high, the cost performance of the method is low. Therefore, the Kostas loop carrier extraction method is mainly studied in this paper.As an application of PLL, Kostas loop plays a very important role in practical carrier synchronization. Firstly, this paper studies the PLL technology deeply, including the structure, working principle and basic performance of PLL.Then the realization method of Kostas loop is studied concretely, and the structure is divided into three modules, which are phase discriminator module.The loop filter module and the DDS module (which are also three main components of the phase-locked loop) are divided into two sub-modules in the realization of the phase discriminator, the multiplier sub-module and the FIR low-pass filter sub-module.After defining the module division, each module is designed and implemented.In this paper, on the ISE hardware development platform developed by Xilinx Company, Verilog HDL hardware description language is used to program. The simulation software is Modelsim SE 6.5. Under the condition that the function simulation of each module reaches the expected goal, the top-level module simulation is started.Finally, the whole program is verified on board with Virtex4 development board, and the final verification result is displayed on oscilloscope.
【学位授予单位】：大连海事大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN967.1

【相似文献】