DVB-S2标准中多模级联纠错码研究及其高速FPGA实现

发布时间：2018-04-05 12:48

本文选题：DVB-S2　切入点：LDPC码　出处：《西安电子科技大学》2014年硕士论文

【摘要】：目前,前向纠错码因其能够有效改善信道噪声对信息传输的影响,在现代数字通信系统中已得到了广泛应用。级联纠错码较单一前向纠错码能够结合外码和内码的各自优势,进一步降低误码率,更接近信道容量。诸多现行的通信标准中采用纠错码级联技术。结合可逼近香农限性能的低密度奇偶校验码(Low Density Parity Check,LDPC)的级联码技术更是该领域的研究热点,欧洲数字电视卫星广播第二代标准(Digital Video Broadcasting Satellite-2nd Generation,DVB-S2)即采用了BCH(Bose Chaudhurl Hocquenghem)+LDPC级联码来进行前向纠错。第二代地面数字电视广播标准(Digital Video Broadcasting-Terrestrial-Second Generation,DVB-T2)、数字视频广播下一代手持终端(Digital Video Broadcast-Next Generation Handheld,DVB-NGH)等标准都将BCH+LDPC级联码作为其前向纠错码。为了适应不同的信道环境,上述通信标准中的级联码多采用多模式方式,如DVB-S2标准中级联码模式多达21种。考虑到DVB-S2标准中BCH+LDPC级联码由于其码长较长、码率较多,不易于硬件实现,本文在不降低其译码性能的前提下,设计了一种基于最小和改进算法高速LDPC译码器的FPGA(Field Programmable Gate Array,可编程逻辑阵列)硬件实现方案。对BCH+LDPC级联码的硬件实现进行了研究,并仿真分析了各模式下级联码的性能。首先,基于Matlab平台,分别仿真了BCH码和LDPC码在AWGN(Additive White Gaussian Noise,加性高斯白噪声)信道下的误比特率性能。特别地,论文对比了不同LDPC译码器算法的复杂度及性能,由对比结果可得,本文采用的译码算法能够在不增加其译码复杂度的条件下对其误码性能最高有0.1dB左右编码增益的提高。其次,论文基于FPGA实现了符合DVB-S2标准的LDPC译码器,并在Xilinx ML605 FPGA芯片上对两种不同译码算法实现的LDPC译码器进行了下载测试。仿真和综合结果表明,在AWGN信道下本文采用的偏置最小和算法(Offset Min-Sum Algorithm,OMSA),基于100MHz工作时钟数据的计算吞吐率最高可达132Mbps,较原算法归一化最小和算法(Normalized Min-Sum Algorithm,NMSA),能够在不增加复杂度的基础上对LDPC译码器的性能有所改善,其误码性能最高可增加0.8dB的编码增益。最后,论文基于FPGA实现了DVB-S2标准BCH+LDPC级联码,并在ML605开发板上下载测试,在AWGN信道下对比了级联前后译码器输出结果。结果表明,对于DVB-S2标准LDPC码中的21种模式,当其误比特率在10-6~10-12之间时,会出现错误平层,而文中BCH+LDPC码级联的实现,BCH码有效降低了LDPC译码器的这一平层,测试区间内误比特率有效下降到10-10以下。
[Abstract]:At present, forward error correction codes have been widely used in modern digital communication systems because they can effectively improve the influence of channel noise on information transmission.Compared with single forward error correction code, concatenated error correction code can further reduce the bit error rate and approach the channel capacity by combining the respective advantages of the outer code and the inner code.Error correction code concatenation is used in many current communication standards.The concatenation technique of low Density Parity check code (LDPC), which can approach the Shannon limit, is a hot research topic in this field.The second Generation Digital Video Broadcasting Satellite-2nd Generation Standard DVB-S2) adopts the BCH(Bose Chaudhurl Hocquenghem-#en5# concatenated code for forward error correction.The second generation digital Video Broadcasting-Terrestrial-Second generation Video Broadcasting-Terrestrial-Second generation DVB-T2C and the next generation digital video broadcasting handheld terminal, digital Video Broadcast-Next Generation handheldor DVB-NGH, take BCH LDPC concatenated code as its forward error correction code.In order to adapt to different channel environments, the concatenated codes in the above communication standards are mostly multi-mode, such as 21 concatenated code modes in the DVB-S2 standard.Considering that the BCH LDPC concatenated code in DVB-S2 standard is not easy to be implemented in hardware because of its long code length and high bit rate, the decoding performance of the concatenated code is not reduced in this paper.A hardware implementation scheme of FPGA(Field Programmable Gate array based on minimum and improved algorithm high speed LDPC decoder is designed.The hardware implementation of BCH LDPC concatenated codes is studied, and the performance of concatenated codes in each mode is simulated and analyzed.Firstly, based on Matlab platform, the BER performance of BCH code and LDPC code in AWGN(Additive White Gaussian Noise (additive Gao Si white noise) channel is simulated respectively.In particular, the complexity and performance of different LDPC decoder algorithms are compared.The decoding algorithm proposed in this paper can improve the performance of 0.1dB code without increasing its decoding complexity.Secondly, based on FPGA, we implement a LDPC decoder that conforms to the DVB-S2 standard, and test the LDPC decoder implemented by two different decoding algorithms on the Xilinx ML605 FPGA chip.Simulation and synthesis results show that,The offset Min-Sum algorithm used in this paper in AWGN channel is offset Min-Sum algorithm. The maximum throughput based on 100MHz working clock data can reach 132 Mbpss, which is higher than that of Normalized Min-Sum algorithm (NMSAA), which can be used for LDPC without increasing complexity.The performance of the decoder has improved,The maximum error performance can increase the coding gain of 0.8dB.Finally, the DVB-S2 standard BCH LDPC concatenated code is implemented based on FPGA, and the test is downloaded on the ML605 development board. The output results of the concatenated decoder are compared under the AWGN channel.The results show that for 21 modes of DVB-S2 standard LDPC codes, the error level will occur when the bit error rate is between 10-6 and 10-12, and the concatenation of BCH LDPC codes can effectively reduce the level layer of LDPC decoder.The bit error rate within the test interval is effectively reduced to below 10-10.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN911.22;TN791

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