应用于全数字锁相环的时间数字转换器的研究与设计

发布时间：2018-04-06 07:21

本文选题：时间数字转换器游标门控环形振荡器　切入点：全数字锁相环　出处：《复旦大学》2014年硕士论文

【摘要】：在射频无线通信领域中,传统的频率综合器基本上都是采用电荷泵锁相环(Charge Pump Phase-Locked Loop)。低电压深亚微米工艺的发展,给数字电路带来了空前的集成度,却使传统射频电路的实现更加复杂困难。近年来,全数字锁相环(All-Digital Phase-Locked Loop, ADPLL)由于可集成度高,可移植性好以及鲁棒性成为了研究的热点。时间数字转换器(Time-to-Digital Converter, TDC)是ADPLL的关键模块,TDC的分辨率决定着ADPLL的带内相位噪声。本文的主要工作是研究设计了一种应用于2.5-5GHz宽带全数字锁相环的门控游标型时间数字转换器。主要研究特色有：1)锁相环在锁定过程中和锁定后对TDC测量范围、分辨率的要求是不同的。锁定过程中对测量范围要求高,对分辨率要求低,锁定后对测量范围的要求低,对分辨率要求高。为了满足锁相环不同状态对TDC测量范围和分辨率的不同要求,所设计的TDC具有两种量化模式——粗量化模式和细量化模式,模式判决电路能根据TDC输入信号幅度的大小自动选择量化模式。2)由于锁相环是分数分频的,在锁定之后,不断变化的分频比会使TDC输入信号的时间间隔增大。为了增加TDC细量化模式的测量范围,使TDC在锁相环锁定后一直工作在细量化模式,TDC的量化单元采用了两级量化结构——第一级为1-bit decision-select,第二级为游标门控环形振荡器(Vernier gated-ring-oscillator, Vernier GRO)。3)在传统的Vernier GRO中,采用SR触发器做比较器制约了Vernier GRO的测量范围和GRO设计的灵活性。本设计采用了一种新型结构的相位比较器,消除了采用SR触发器做比较器对测量范围的制约,提高了GRO设计的灵活性。芯片采用TSMC 0.13μm工艺实现,电源电压为1.2V,测试结果表明,TDC的采样频率不低于40MHz,粗量化模式的测量范围不小于25ns,细量化模式的测量范围为1.8ns。应用于ADPLL中,在3.68GHz频率处,环路的带内相位噪声为-92dBc/Hz@5kHz,对应的TDC有效分辨率为23ps。
[Abstract]:In the field of RF wireless communication, the traditional frequency synthesizers are basically charge Pump Phase-Locked Loopers.The development of low-voltage deep submicron technology brings unprecedented integration to digital circuits, but it makes the realization of traditional RF circuits more complex and difficult.In recent years, All-Digital Phase-Locked Loop (ADPLL) has become a hotspot for its high integration, good portability and robustness.Time-to-digital converter (TDC) is a key module of ADPLL. The resolution of TDC determines the in-band phase noise of ADPLL.The main work of this paper is to study and design a gated Vernier time Digital Converter (TDC) for 2.5-5GHz wideband all-digital phase-locked loop (DPLL).The main research features are: (1) TDC measurement range and resolution requirements are different in the process of locking and after locking.In the process of locking, the requirement of measuring range is high, the requirement of resolution is low, the requirement of measurement range is low after locking, and the requirement of resolution is high.In order to meet the different requirements of TDC measurement range and resolution in different states of PLL, the designed TDC has two quantization modes: coarse quantization mode and fine quantization mode.The mode decision circuit can automatically select quantization mode. 2 according to the magnitude of the TDC input signal. Because the phase-locked loop is fractional frequency division, the time interval of the TDC input signal will be increased by changing frequency division ratio after locking.In order to increase the measurement range of the TDC fine quantization mode,The quantization unit that causes TDC to work in fine quantization mode after PLL locking adopts a two-level quantization structure-the first stage is 1-bit decision-selectand the second stage is Vernier gated-roscing-illator.3) in the traditional Vernier GRO, the Vernier gated-roscing-illator (Vernier GROT. 3) is the first level of quantization, and the second stage is Vernier gated-roscillator (Vernier. 3).Using SR flip-flop as comparator restricts the measurement range of Vernier GRO and the flexibility of GRO design.A new structure phase comparator is used in this design, which eliminates the restriction of measuring range by SR flip-flop and improves the flexibility of GRO design.The chip is realized by TSMC 0.13 渭 m technology and the power supply voltage is 1.2 V. the test results show that the sampling frequency is not less than 40MHz, the measurement range of coarse quantization mode is not less than 25ns, and the measurement range of fine quantization mode is 1.8ns.In ADPLL, the in-band phase noise of the loop is -92 dBc / Hz @ 5kHz at the 3.68GHz frequency, and the corresponding TDC effective resolution is 23ps.
【学位授予单位】：复旦大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN911.8

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