基于Handel-C的H.264帧内编码算法硬件化设计

发布时间：2018-04-14 13:35

本文选题：H.264 + FPGA　；参考：《西安电子科技大学》2014年硕士论文

【摘要】：随着信息化的不断发展,人类社会对于多媒体尤其是视频信息的需求不断增多,视频在会议、网络点播等诸多应用领域得到快速发展,在此同时,对视频质量的要求也在不断提高。视频数量的急剧增加以及视频质量需求的提高,使得视频存储以及传输的数据量急剧增大,但是网络带宽以及存储空间是有限的,因此实现视频的高效存储和传输成为实时视频处理的一个关键问题。通过H.264技术的高压缩率,极大减小了视频的存储和传输过程中占用的资源,但是,其高压缩比是通过大量的运算获得的,会增加系统的运行时间。现在,FPGA技术的快速发展为实时视频处理提供了良好的解决办法。FPGA等硬件平台高速并行化的特点,以及廉价和具有丰富逻辑资源的新型FPGA器件的出现,为视频压缩的并行化处理提供了良好的条件。论文首先研究了H.264视频编解码标准及其编码原理,重点分析了编码层实现的主要技术以及影响编码效率的关键因素,对本文所要研究及实现的算法原理及实现方法进行了重点介绍,明确了设计过程中所要解决算法中的关键问题。然后阐述了基于FPGA平台设计的一般方法及Handel-C并行化硬件语言,基于该语言相对于传统语言具有实现快速、代码简洁以及适合软件工程师使用的特点,提出了使用该语言的H.264帧内编码设计方法。其次,根据H.264编码层帧内预测内部结构及工作原理,分析了帧内算法及设计流程,设计了帧内预测算法整体的硬件化结构及功能模块接口。随后采用Handel-C设计语言对H.264帧内编码各个主要功能模块进行了详细设计,完成了16×16分块、4×4分块、8×8分块下的帧内各种模式预测和整数变换、量化等模块的设计实现,并将各模块整合以实现模式选择,完成了编码算法中预测、重构以及模式选择等过程。建立设计模块的波形仿真文件,对所设计模块进行功能仿真。同时,在设计中充分利用Handel-C的语句并行化,提高了算法的执行效率。最后对所设计的功能模块进行了模块综合以及仿真验证。经实验结果分析,使用Handel-C可以进行FPGA平台上的H.264算法设计以及实现并可以取得良好的运算性能,验证了该语言在FPGA平台上实现视频压缩部分算法硬件化的可行性。论文工作对以后其他基于Handel-C高级语言的算法硬化设计以及视频算法的并行设计具有借鉴意义。
[Abstract]:With the continuous development of information technology, the demand for multimedia, especially video information is increasing in human society. Video has been developed rapidly in many application fields, such as conference, network on demand and so on. At the same time,Video quality requirements are also constantly improving.With the rapid increase of video quantity and the improvement of video quality demand, the amount of video storage and transmission data increases rapidly, but the network bandwidth and storage space are limited.Therefore, the efficient storage and transmission of video becomes a key problem in real-time video processing.The high compression ratio of H.264 greatly reduces the resources consumed in the process of video storage and transmission. However, the high compression ratio is obtained by a large number of operations, which will increase the running time of the system.Now the rapid development of FPGA technology provides a good solution for real-time video processing. FPGA and other hardware platform high-speed parallelization characteristics, as well as cheap and rich logic resources of the emergence of new FPGA devices,It provides a good condition for parallel processing of video compression.Firstly, the H.264 video coding and decoding standard and its coding principle are studied, and the main techniques of the coding layer and the key factors affecting the coding efficiency are analyzed.This paper mainly introduces the principle and method of the algorithm which is to be studied and realized in this paper, and clarifies the key problems to be solved in the process of design.Then the general method of design based on FPGA platform and the parallel hardware language of Handel-C are introduced. Compared with the traditional language, the language has the characteristics of fast realization, simple code and suitable for software engineers.A design method of H. 264 intra coding using this language is presented.Secondly, according to the internal structure and working principle of intra prediction in H.264 coding layer, the intra algorithm and its design flow are analyzed, and the hardware structure and function module interface of the whole intra prediction algorithm are designed.Then, the main function modules of H. 264 intra coding are designed in detail by using Handel-C design language, and the design and implementation of various mode prediction, integer transformation and quantization modules under 16 脳 16 block 4 脳 4 block and 8 脳 8 block are completed.The modules are integrated to realize pattern selection, and the process of prediction, reconstruction and pattern selection in coding algorithm is completed.The waveform simulation file of the design module is established, and the function of the designed module is simulated.At the same time, the parallelization of Handel-C sentences is fully utilized in the design, and the efficiency of the algorithm is improved.Finally, the module synthesis and simulation verification of the designed functional module are carried out.The experimental results show that the H.264 algorithm on FPGA platform can be designed and implemented by using Handel-C, and good performance can be achieved. The feasibility of the hardware implementation of video compression algorithm on FPGA platform is verified.The work of this paper can be used for reference to other algorithms hardening design based on Handel-C and concurrent design of video algorithms.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN919.81

【参考文献】