块浮点脉冲压缩及其关键IP核的设计与实现

发布时间：2018-04-20 16:14

本文选题：块浮点 + 脉冲压缩　；参考：《西安电子科技大学》2014年硕士论文

【摘要】：雷达在现代军用、民用的多个领域内起着主导作用,其中雷达信号处理的性能也起着比较关键的作用。随着雷达信号处理和超大规模集成电路的不断发展,为了适应多种工作环境和多种工作模式,为了能够处理更大动态范围内的数据,并提高数据处理精度,雷达数字信号处理中的数据处理不再单纯的采用定点数据,而逐渐向浮点数据处理方向发展,但是浮点数据处理的硬件资源消耗比较大,在这种情况下,为了在一定程度上提高数据处理的动态范围,块浮点数据成为了平衡动态范围和硬件面积的一种折中选择。雷达信号处理中的脉冲压缩技术解决了雷达发射信号功率与雷达距离分辨率之间的矛盾,因此得到了广泛的应用。本文主要研究脉冲压缩的硬件实现。本论文使用块浮点数据格式,对雷达信号处理中的脉冲压缩系统及其关键的快速傅里叶变换和逆变换(FFT/IFFT)的ASIC实现进行了设计和优化。首先,介绍了雷达信号处理中的脉冲压缩、FFT/IFFT的原理和块浮点数据的硬件实现形式;然后结合FFT/IFFT的硬件实现原理,设计了适用于块浮点数据处理的输入输出数据类型可配置,FFT/IFFT运算的点数可调整的FFT/IFFT IP核,并重点研究了减小硬件面积的数据存储规律和块浮点数据的处理过程,采用了内部数据倍频处理的方式,使得系统的利用率提高并减小硬件面积。结合本设计的FFT/IFFT IP核,进行了输入输出数据类型可配置,处理数据长度可配置的块浮点脉冲压缩系统的规划,并设计了一种脉冲压缩的处理方法,研究了其存储规律及其四路匹配相乘规律,从而减小了脉冲压缩处理的延时,最终完成了四路可配置的块浮点脉冲压缩处理单元的RTL设计。本论文使用Matlab和Modelsim对设计的RTL级的四路脉冲压缩块浮点处理器进行了功能验证;分析了FFT/IFFT单元的数据处理相对误差在10-6数量级、信噪比在200 dB左右;同时对本设计的四通路脉冲压缩系统的处理延时进行了分析;使用FPGA对其进行验证;在SMIC 0.13μm工艺环境下,使用Design Compiler#174;进行逻辑综合,该脉压处理器的内部工作频率为200 MHz,I/O系统时钟频率为100MHz;使用Formality#174;对逻辑综合的网表进行了形式验证,并使用Prime Time#174;对其进行了静态时序分析。
[Abstract]:Radar plays a leading role in many fields of modern military and civil, among which the performance of radar signal processing also plays a key role. With the continuous development of radar signal processing and VLSI, in order to adapt to a variety of working environments and modes, to be able to process data in a larger dynamic range, and to improve the accuracy of data processing, The data processing in radar digital signal processing is no longer simply using fixed-point data, but gradually developing to floating-point data processing, but the hardware resources of floating-point data processing are relatively large, in this case, In order to improve the dynamic range of data processing to a certain extent, the block floating point data has become a compromise choice to balance the dynamic range and the hardware area. The pulse compression technique in radar signal processing solves the contradiction between the power of radar signal and the range resolution of radar, so it has been widely used. This paper mainly studies the hardware implementation of pulse compression. In this paper, the pulse compression system in radar signal processing and its key fast Fourier transform (FFT) and inverse transform (FT / IFFTFT) ASIC implementation are designed and optimized by using block floating-point data format. Firstly, the principle of pulse compression FFT / Ifft and the hardware realization of block floating-point data in radar signal processing are introduced, and then the hardware implementation principle of FFT/IFFT is combined. A configurable FFT/IFFT IP core suitable for block floating-point data processing is designed, which can be configured for FFT / Ifft operation. The rules of data storage for reducing hardware area and the processing process of block floating-point data are studied. The internal data frequency doubling method is used to improve the utilization ratio of the system and reduce the hardware area. Combined with the FFT/IFFT IP core designed in this paper, a block floating point pulse compression system with configurable input and output data type and configurable data length is designed, and a pulse compression processing method is designed. The storage law and the four-way matching multiplication rule are studied, which reduces the delay of pulse compression processing, and finally completes the RTL design of four-channel configurable block floating-point pulse compression processing unit. In this paper, Matlab and Modelsim are used to verify the function of the four-channel pulse compression block floating-point processor designed for RTL, and the relative error of data processing for FFT/IFFT unit is in the order of 10-6, and the SNR is about 200dB. At the same time, the processing delay of the four-way pulse compression system is analyzed, the FPGA is used to verify it, the Design Compiler #174 is used in the SMIC 0.13 渭 m process, and the logic synthesis is carried out. The internal working frequency of the pulse compression processor is 200 MHz / I / O system clock frequency is 100 MHz; the formal #174 is used; the network table of logic synthesis is formally verified and the Prime time #174 is used; the static timing analysis is carried out.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN957.51

【引证文献】