QAM信号的位同步与盲均衡实现技术研究

发布时间：2018-04-22 20:26

本文选题：QAM + 位同步　；参考：《电子科技大学》2014年硕士论文

【摘要】：数字基带通信系统接收端的基本功能是正确接收发送端传来的数据,完成与发送端对应的反变换,包括解调,解密和译码等环节,最后恢复出信源产生的数据交给信宿。接收端为了正确接收数据,需要与发送端保持位定时的一致,信道的带限特性会引起传输的信号的码间干扰,给抽样判决带来影响。包括位同步算法和均衡算法在内的基带算法成为接收端的核心内容,其中,位同步算法决定了基带系统的位定时是否准确快速;均衡算法决定了数据在有码间干扰的情况下能否正确传输,因此,研究基带传输系统中的位同步和均衡具有重要的研究意义。本文基于FPGA的硬件平台,研究和设计了在频分双工(Frequency Division Duplexing,FDD)传输模式下,以正交幅度调制(QAM)为信号调制方式,数据传输速率达到80Mbps的基带传输系统,并着重设计和实现了接收端的位同步算法以及盲均衡算法。本文的主要工作如下:首先介绍了基带通信系统的整体框架,包括扰码编码、差分编码、电平映射以及成型滤波模块等。接着,详细研究了和设计了基带接收端的位同步算法以及盲均衡算法。针对位同步算法,先着重介绍了Gardner定时误差检测算法的基本原理,然后搭建位同步环路的Simulink模型,通过定点仿真确定合适的参数设置,最后用Verilog语言编写相应的模块,完成功能测试以及板级验证;而盲均衡算法采用的是改进的双模式恒模算法(MCADAMA),其设计思路和步骤与位同步模块类似。在位同步算法和盲均衡算法实现的基础上,本文进行了整个基带传输系统在FPGA上的连调与测试。测试结果证明,本文中设计的位同步与盲均衡算法的实现方案是可行的,其达到的接收性能符合项目要求。
[Abstract]:The basic function of the receiver of the digital baseband communication system is to receive the data from the transmitter correctly, complete the inverse transformation corresponding to the transmitter, including demodulation, decryption and decoding, and finally restore the data generated by the source to the receiver. In order to receive the data correctly, the receiver needs to be consistent with the bit timing of the transmitter. The band-limit characteristic of the channel will cause the inter-symbol interference of the transmitted signal and affect the sampling decision. The base-band algorithm including bit synchronization algorithm and equalization algorithm becomes the core of the receiver. The bit synchronization algorithm determines whether the bit timing of the baseband system is accurate and fast. The equalization algorithm determines whether the data can be transmitted correctly in the presence of inter-symbol interference. Therefore, it is of great significance to study bit synchronization and equalization in baseband transmission systems. Based on the hardware platform of FPGA, this paper studies and designs a baseband transmission system with quadrature amplitude modulation (QAM) as signal modulation mode and data transmission rate up to 80Mbps in frequency division duplex Division duplex mode. The bit synchronization algorithm and blind equalization algorithm are designed and implemented. The main work of this paper is as follows: firstly, the whole frame of baseband communication system is introduced, including scrambling coding, differential coding, level mapping and shaping filter module. Then, the bit synchronization algorithm and blind equalization algorithm of baseband receiver are studied and designed in detail. For bit synchronization algorithm, the basic principle of Gardner timing error detection algorithm is introduced, then the Simulink model of bit synchronization loop is built, and the appropriate parameter setting is determined by fixed-point simulation. Finally, the corresponding module is written in Verilog language. The Blind equalization algorithm uses an improved dual-mode constant modulus algorithm, MCADAMAA, and its design idea and steps are similar to that of the bit synchronization module. Based on the realization of bit synchronization algorithm and blind equalization algorithm, the whole baseband transmission system is tested on FPGA. The test results show that the proposed bit-synchronization and blind equalization algorithm is feasible and the received performance meets the requirements of the project.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN914.3

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