超宽带低相噪频综研究

发布时间：2018-04-24 01:09

本文选题：晶体管参量倍频 + DDS　；参考：《电子科技大学》2015年硕士论文

【摘要】：现代战争是科技的战争,随着军事通信中人为干扰因素越来越严重,对通信设备的抗干扰性能的要求越来越高。其中,跳频通信技术在抗干扰、抗截获方面有着巨大的优越性。跳频通信系统中,频综是其核心部件,频综的性能直接影响跳频系统的抗干扰、抗截获能力。本论文介绍了跳频通信系统中核心部件频综的各种实现方法。通过对晶体管倍频、DDS(直接数字频率合成)、PLL(锁相环)基本方法实现频率合成器的理论研究,分析各自优缺点,得出一种倍频器、DDS、PLL相结合实现频综的方案;倍频器输出作为DDS的参考系统时钟,而DDS的输出又作为PLL的参考频率,结合它们的优点,避开它们的缺点,从而使频综整体性能更好。其中,倍频器是基于MRF851晶体管的C类参量倍频器,利用契比雪夫带通滤波器对不需要的谐波滤波;倍频器输出作为基于AD9910的DDS的参考时钟,针对DDS输出杂散多的问题,设计了带宽只有30KHz的单片晶体滤波器,对DDS输出进行窄带滤波;DDS输出又作为基于HMC704LP4鉴相芯片的PLL的参考频率,最后实现频综输出;通过设计频综控制程序,将输出频率进行分段,段内跳频只需改变DDS频率控制字,使跳频时间非常短,段间跳频需同时改变DDS和PLL频率控制字,跳频时间稍长。对频综系统电源及腔体进行了电磁兼容设计,各模块分腔处理,最终实现了频率范围从1850MHz~3075MHz的频综,频综相位噪声低于-100 dBc/Hz@10 KHz,杂散抑制度优于-74d Bc,跳频时间小于100?s,频率步进为10 KHz。可以看出该频综的整体指标较好,满足跳频系统中对频综的需求。
[Abstract]:Modern war is the war of science and technology. With the more and more serious human interference factors in military communication, the anti-interference performance of communication equipment is becoming more and more high. Among them, frequency-hopping communication technology has great superiority in anti-jamming and anti-interception. In frequency hopping communication system, frequency ensemble is the core component. The performance of frequency synthesizer directly affects the anti-jamming and anti-interception ability of frequency hopping system. This paper introduces a variety of implementation methods of frequency synthesis of core components in frequency hopping communication system. Through the theoretical research on the realization of frequency synthesizer based on DDS (Direct Digital Frequency synthesizer PLL) method, the advantages and disadvantages of the frequency synthesizer are analyzed, and a scheme of frequency synthesizer based on the combination of frequency multiplier and DDS / PLL is obtained. The frequency multiplier output is used as the clock of the DDS reference system, and the DDS output is the reference frequency of the PLL. By combining their advantages and avoiding their disadvantages, the overall performance of the frequency synthesizer is better. The frequency multiplier is a class C parametric frequency multiplier based on MRF851 transistor, which uses Chebyshev band-pass filter to filter the unwanted harmonics, and the frequency multiplier output is used as the reference clock of DDS based on AD9910, aiming at the problem that DDS output has more spurious output. A single-chip crystal filter with bandwidth only 30KHz is designed, and the output of DDS is used as the reference frequency of PLL based on HMC704LP4 phase discriminator. Finally, the frequency synthesizer output is realized, and the frequency synthesizer control program is designed. When the output frequency is segmented, the frequency hopping in the segment only needs to change the DDS frequency control word, so the frequency hopping time is very short, and the DDS and PLL frequency control words need to be changed at the same time between the segments. The frequency hopping time is a little longer. The electromagnetic compatibility design of the power supply and cavity of the frequency synthesizer system is carried out. The frequency range from 1850MHz~3075MHz to frequency synthesizer is realized. The phase noise of the frequency ensemble is lower than -100 dBc/Hz@10 KHz, the spurious suppression degree is better than -74 d Bc, the frequency hopping time is less than 100 kHz, and the frequency step is 10 kHz. It can be seen that the overall index of the frequency synthesizer is better and meets the need of frequency synthesis in the frequency hopping system.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN914.41

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