基于FPGA和DSP的图像压缩系统实现方法研究

发布时间：2018-04-25 13:52

本文选题：图像压缩 + JPEG2000　；参考：《中北大学》2014年硕士论文

【摘要】：图像信号具有直观、形象、易懂和信息量大等特点，是人们最丰富的信息来源。然而图像数字化后的数据量太大，对数据的传输、存储等方面具有很大的挑战，所以，传统的图像传感器、采集卡、计算机显示的模式已经远远不能满足要求，对图像的实时编码压缩显得尤为重要。本文综合考虑了FPGA处理速度快和DSP在算法方面突出的优势，，提出了通过FPGA控制图像的采集、缓存、格式的转换、前期的处理以及与计算机之间的数据传输，通过DSP实现JPEG2000算法，对图像进行压缩的方案。同时，为了适应多种图像的输入，本系统设计了多种视频图像输入接口，包括传统的模拟视频输入CVBS混合视频输入和S-video输入，还可以实现Camera Link数字接口的视频输入。图像采集前端通过FPGA的I/O端口模拟I2C总线时序，完成对视频解码器的初始化配置，并接收其输出的标准数字视频格式ITU-R BT.656的图像数据，对该数据进行格式的变换以及一些前期的处理后，传输给DSP进行实时的压缩。此外，FPGA还控制与计算机的接口，接收计算机的指令，并将压缩后的图像数据传输给计算机。压缩编码模块采用了TI公司的C6000系列DSP，在硬件上实现了JPEG2000算法，对图像进行了实时压缩。最后通过实验，验证并比较了图像压缩的效果，并对算法进行了部分改进。该系统实用性强，稳定性高，在高压缩比的情况下图像失真率低，无论是在工业控制领域还是科研方面都有一定的借鉴意义。
[Abstract]:Image signal is the most abundant source of information because it is intuitive, image, easy to understand and large amount of information. However, the amount of digital image data is too large, the data transmission, storage and other aspects have a great challenge, so the traditional image sensor, acquisition card, computer display mode has been far from meeting the requirements. It is very important to compress the image in real time. Considering the fast processing speed of FPGA and the outstanding advantages of DSP in algorithm, this paper puts forward that the JPEG2000 algorithm can be realized by DSP, which can control image acquisition, cache, format conversion, pre-processing and data transmission with computer. The scheme of image compression. At the same time, in order to adapt to the input of various images, the system designs a variety of video input interfaces, including the traditional analog video input CVBS mixed video input and S-video input, and can also realize the Camera Link digital interface video input. The image acquisition front-end simulates the I2C bus timing through the I / O port of FPGA, accomplishes the initialization configuration of the video decoder, and receives the image data of the standard digital video format ITU-R BT.656. The data is transmitted to DSP for real-time compression after format transformation and some previous processing. In addition, FPGA also controls the interface with the computer, receives instructions from the computer, and transmits the compressed image data to the computer. The compression coding module adopts TI C6000 series DSP and implements the JPEG2000 algorithm in hardware. The image is compressed in real time. Finally, the effect of image compression is verified and compared by experiments, and the algorithm is partially improved. The system has strong practicability, high stability and low image distortion rate under the condition of high compression ratio. It has some reference significance in both industrial control field and scientific research.
【学位授予单位】：中北大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN919.81

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