面向雷达应用的粗粒度可重构处理器中配置通路子系统的设计与优化

发布时间：2018-04-29 17:07

本文选题：粗粒度可重构处理器 + 雷达应用　；参考：《东南大学》2015年硕士论文

【摘要】：兼具高性能与灵活性的粗粒度可重构处理器,特别适于实现数据量大且计算密集的雷达信号处理过程。然而,随着雷达性能需求的不断增长,可重构处理器的计算资源成倍增加,使得配置信息量随之变大、配置传输时间急剧增长,重构效率低最终导致可重构处理器无法展现其计算性能优势。因此,建立高效的配置管理机制对于可重构处理器十分重要。本文针对配置通路子系统中配置信息量大引起的配置传输时间长的问题,依次开展了下述几项工作以提高重构效率：一、分析了雷达信号处理过程,提取了其中的核心算法,并结合可重构处理器的硬件结构特点为核心算法选择了合适的实现方案、进行了运算过程优化：二、基于层次化配置存储结构,设计了RASP配置通路子系统的基本结构,说明了其工作方式,并评估了它的配置缓存访问性能及配置传输性能；三、分析了雷达核心算法的配置流特性,挖掘了算法多个并行任务的配置信息冗余规律以及算法子任务的配置信息冗余规律,并根据前者提出了配置信息的分级组织策略：四、基于雷达核心算法一个子任务的配置信息冗余规律,设计了一种基于动态模式匹配的配置压缩方法,在配置压缩时动态提取算法数据流图中重复出现的基本单元的配置信息,并在解压缩时将其动态匹配到阵列上以得到完整的初始配置信息,在有效控制动态解压缩时间的同时,大幅缩减了配置信息量。实验结果表明,在SMIC 40nm工艺下,主频为500MHz时,针对雷达核心算法,本文的配置信息分级组织策略以及基于动态模式匹配的压缩方法,可将阵列配置信息量缩减到原来的40%以下且解压缩时间仅需6 ns。在配置缓存开销减少25%的情况下,配置组缓存命中率提升了5%-8%,阵列配置缓存命中率提升了5%-16%,RASP的重构性能提升到原来的2.60倍以上,高于SIMD和字典压缩方法。对于同点数FFT运算,优化后RASP的性能是其他可重构处理器的5倍以上,对于同阶数矩阵求逆运算,优化后RASP的性能是其他可重构处理器的3倍以上,且RASP在很大的参数范围内都能取得较好的性能,系统灵活性较好。
[Abstract]:Coarse-grained reconfigurable processors with high performance and flexibility are especially suitable for radar signal processing with large amount of data and dense computation. However, with the increasing demand for radar performance, the computing resources of the reconfigurable processor increase exponentially, resulting in the increase of configuration information and the rapid increase of configuration transmission time. The low reconfiguration efficiency ultimately leads to the inability of the reconfigurable processor to demonstrate its computing performance advantages. Therefore, it is very important to establish efficient configuration management mechanism for reconfigurable processors. Aiming at the problem of long configuration transmission time caused by the large amount of configuration information in the configuration passageway sub-system, this paper has carried out the following work in turn to improve the reconstruction efficiency: firstly, the radar signal processing process is analyzed, and the core algorithm is extracted. Combined with the hardware structure characteristics of the reconfigurable processor, this paper selects the appropriate implementation scheme for the core algorithm, and optimizes the operation process. Secondly, based on the hierarchical configuration storage structure, the basic structure of the RASP configuration pass-through sub-system is designed. Its working mode is explained, and its configuration cache access performance and configuration transmission performance are evaluated. Thirdly, the configuration flow characteristics of radar core algorithm are analyzed. The redundancy rule of configuration information of multiple parallel tasks and the redundancy rule of configuration information of algorithm sub-task are excavated. According to the former, the hierarchical organization strategy of configuration information is put forward: fourth, Based on the redundancy rule of configuration information of a sub-task of the radar core algorithm, a configuration compression method based on dynamic pattern matching is designed to dynamically extract the configuration information of the basic units repeated in the data flow diagram of the algorithm. The initial configuration information can be obtained by matching it to the array dynamically during decompression, which can effectively control the dynamic decompression time and greatly reduce the amount of configuration information. The experimental results show that when the main frequency is 500MHz in the SMIC 40nm process, the configuration information hierarchical organization strategy and the compression method based on dynamic pattern matching are proposed for the radar core algorithm. The array configuration information can be reduced to less than 40% and the decompression time is only 6 NS. Under the condition of 25% reduction of configuration cache overhead, the hit ratio of configuration group cache increases 5-8, and the hit rate of array configuration cache increases by more than 2.60 times than that of SIMD and dictionary compression method. For the same number of FFT operations, the performance of optimized RASP is more than 5 times that of other reconfigurable processors, and the performance of optimized RASP is more than 3 times that of other reconfigurable processors for the inverse operation of the same order matrix. RASP can achieve better performance in a wide range of parameters, and the system is flexible.
【学位授予单位】：东南大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN957.51

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