基于线性增强TDC的全数字锁相环设计

发布时间：2018-05-03 21:10

  本文选题：全数字锁相环 + 线性增强算法　； 参考：《电子科技大学》2014年硕士论文

【摘要】：锁相环作为片内高速时钟的提供者,在现代电路中至关重要,几乎所有的大规模数字电路都会用到锁相环。传统的锁相环的性能和面积受到其含有的模拟电路的限制。数字集成电路抗干扰能力强、可移植性好、面积小和功耗低等优点使全数字的锁相环得以广泛应用。时间数字转换器(TDC)是全数字锁相环(ADPLL)的重要组成部分,它的分辨率决定了锁相环输出信号频率与参考信号频率的接近程度,其动态范围决定了锁相环的捕获范围和锁定时间。本文采用计数器和延时链混合结构的TDC,该结构使TDC满足高分辨率的同时具有宽的动态范围。针对TDC的延时链,本文提出了一种线性增强算法,对TDC的积分非线性有很大改善。本文首先简单介绍了锁相环的历史和研究意义,对全数字锁相环与传统锁相环的优缺点进行了比较。然后对锁相环的工作原理、结构和数学模型进行了介绍,并对全数字锁相环的工作原理和各个模块,包括鉴频鉴相器(PFD)、时间数字转换器(TDC)、数字环路滤波器(DLF)和数控振荡器(DCO)等的结构和数学模型进行了详细阐述。重点的介绍了线性增强TDC的工作原理和设计。最后本文对所设计的全数字锁相环及各个子模块的设计和仿真进行了详细描述。本文设计的全数字锁相环采用的是0.18μm CMOS工艺,完成了所有电路的设计和仿真,且全数字锁相环路的输出频率能够正常锁定,环路的锁定时间为2μs,其输出频率为250MHz,峰峰抖动为76ps。
[Abstract]:Phase locked loop (PLL) is very important in modern circuits as the provider of high speed clock in chip. Almost all large scale digital circuits use PLL. The performance and area of traditional PLL are limited by its analog circuit. Digital integrated circuit has the advantages of strong anti-jamming ability, good portability, small area and low power consumption. Time digital converter (TDC) is an important part of all digital phase-locked loop (ADPLL). Its resolution determines the proximity between the output signal frequency and the reference signal frequency, and its dynamic range determines the capture range and locking time of the phase-locked loop. In this paper, TDC with the mixed structure of counter and delay chain is used, which makes the TDC meet the high resolution and has a wide dynamic range. For the delay chain of TDC, a linear enhancement algorithm is proposed, which greatly improves the integral nonlinearity of TDC. In this paper, the history and research significance of PLL are briefly introduced, and the advantages and disadvantages of full digital PLL and traditional PLL are compared. Then the working principle, structure and mathematical model of the PLL are introduced, and the working principle and each module of the all-digital PLL are introduced. The structure and mathematical model of the phase discriminator, time digital converter (TDC), digital loop filter (DLF) and numerical control oscillator (DCO) are described in detail. The working principle and design of linear enhanced TDC are introduced emphatically. Finally, the design and simulation of all digital PLL and its sub-modules are described in detail. The all-digital phase-locked loop designed in this paper uses 0.18 渭 m CMOS technology. All circuits are designed and simulated. The output frequency of the all-digital phase-locked loop can be locked normally. The locking time of the loop is 2 渭 s, the output frequency is 250MHz, and the peak jitter is 76ps.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN911.8
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本文编号：1840092