基于FPGA的LDPC编译码系统的研究

发布时间：2018-05-05 10:29

本文选题：FPGA + QC-LDPC　；参考：《北京交通大学》2014年硕士论文

【摘要】：摘要：信道编码一直以来就是通信届研究的一个热点,自从LDPC码问世以来,一直成为人们研究的热点,LDPC码具有灵活的校验矩阵构造、良好的纠错性能而且译码复杂度低、译码吞吐率高的特点。随着无线局域网技术,超大光纤容量的发展,在信道上为了使信息能够更准确的传输,对信道编码技术要求很高。如今LDPC码被IEEE802.11n标准采纳为信道编码的一种方案,并且在未来的第四代OFDM通信系统中得到广泛应用。本文正是在IEEE802.11n的标准下,以FPGA为开发平台采用准循环的编码结构来设计编译码器。准循环QC-LDPC码具有良好的纠错性能以及便于用硬件实现,目前LDPC码译码算法种类较多,本文在研究各种译码算法的基础上,选择了一种最佳的译码算法作为研究对象,并且用Xilinx公司开发的FPGA芯片对算法进行验证。主要工作如下：首先,介绍LDPC码的相关背景知识以及LDPC编码和译码的基本原理以及FPGA开发技术。其次,在确定了校验矩阵之后要确定编译码的算法,在matlab环境下建立仿真模型,对编译码的性能做出分析,选定最佳的设计算法。同时算法设计完成之后确定一个用于FPGA的设计方案,将其在ISE14.1开发工具下用verilog语言对编译码的算法进行功能仿真,最后将整个系统进行综合在FPGA开发板上做验证,将译码器的输出结果与matlab的译码结果作对比,以便得出结论设计实现结果表明,译码器在时序、资源占用以及性能上满足系统要求。
[Abstract]:Absrtact: Channel coding has always been a hot topic in the field of communication. Since the advent of LDPC codes, it has been a hot research topic. It has flexible construction of check matrix, good error-correcting performance and low decoding complexity. High throughput in decoding. With the development of wireless local area network (WLAN) technology and large fiber capacity, channel coding technology is required in order to transmit information more accurately on the channel. Now LDPC code is adopted as a channel coding scheme by IEEE802.11n standard, and it is widely used in the fourth generation OFDM communication system in the future. In this paper, based on the standard of IEEE802.11n, the quasi-cyclic coding structure is adopted to design the codec based on FPGA. Quasi-cyclic QC-LDPC codes have good error-correcting performance and are easy to implement in hardware. At present, there are many kinds of decoding algorithms for LDPC codes. Based on the study of various decoding algorithms, this paper selects an optimal decoding algorithm as the research object. The algorithm is verified by FPGA chip developed by Xilinx Company. The main tasks are as follows: Firstly, the background of LDPC code, the basic principle of LDPC coding and decoding, and the FPGA development technology are introduced. Secondly, after determining the check matrix, the algorithm of encoding and decoding should be determined, and the simulation model should be established in matlab environment, the performance of encoding and decoding should be analyzed, and the best design algorithm should be selected. At the same time, after the algorithm design is completed, a design scheme for FPGA is determined, which is simulated by verilog language under the ISE14.1 development tool. Finally, the whole system is synthesized on the FPGA development board to verify. The output of the decoder is compared with the decoding result of matlab, and the design and implementation results show that the decoder meets the requirements of the system in timing, resource occupation and performance.
【学位授予单位】：北京交通大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN911.22

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