基于FPGA的高速Turbo乘积码技术及其实现

发布时间：2018-05-12 17:10

本文选题：Turbo乘积码 + 分组BCH码　；参考：《西安电子科技大学》2014年硕士论文

【摘要】：在信道编码理论的发展历程中,1994年提出的Turbo乘积码是一种高效的信道编码技术,其在码率、误码性能和硬件复杂度等方面拥有显著的优点,因此逐渐成为信道编码研究的热点。乘积码相比于同码率的Turbo码具有更接近于Shannon限的渐近性能。随着通信领域的不断发展,深空通信和移动通信领域对通信系统的可靠性和高效性的要求越来越高。在TPC的应用与硬件实现方面,乘积码因其优异的纠错性能和相对简单的编译码算法,得到了越来越广泛的应用。本文首先详细介绍了TPC的编码原理和分量码的选择,同时阐述了Chase译码算法,并且描述了通过测试序列快速译码、节省存储资源、减少候选码字个数、无竞争码字时的外信息计算方法和提高译码器并行度的改进的译码算法,分析了改进译码算法的优势,对译码性能进行了理论分析。此外,本文通过软件构造了通信系统的仿真模型,验证分析了不同的分量码、迭代次数、不可靠位置数、量化比特数和信道类型对于TPC译码性能的影响,同时对改进型译码算法进行了仿真验证和性能分析。最后重点描述了TPC编译码器的FPGA实现,并详细介绍了编译码器的主要构造及改进的方案。整个译码器采用了一种全并行输入的分量码译码器,该分量码译码器可以完成对整个分量码输入、比较排序选取不可靠位置、排列候选码字的度量值和计算外信息,极大地增加了译码的并行度,减少了译码的时延,有效的提高了系统的吞吐量。本文采用Xilinx公司生产的Kintex-7系列中的XC7K355T芯片完成整个设计。整个设计占用芯片39%的逻辑资源和35%的存储资源,完成了一种综合型译码器,该综合型译码器完成对(1024,676)、(2048,1824)和(4096,3249)三种码的译码工作。对于(1024,676)码而言,译码器的吞吐量可达T=274.80Mbps。对于(4096,3249)码而言,译码器的吞吐量可达T=571.34Mbps。
[Abstract]:In the course of the development of channel coding theory, Turbo product code proposed in 1994 is an efficient channel coding technology. It has significant advantages in bit rate, error rate and hardware complexity, so it has gradually become a hot research topic in channel coding. The product codes have the asymptotic performance closer to the Shannon limit than the Turbo codes at the same rate. With the development of communication field, the requirement of reliability and efficiency of communication system in deep space communication and mobile communication field is more and more high. In the aspect of application and hardware implementation of TPC, product codes are more and more widely used because of their excellent error-correcting performance and relatively simple encoding and decoding algorithms. In this paper, the coding principle of TPC and the selection of component codes are introduced in detail. At the same time, the algorithm of Chase decoding is expounded, and the fast decoding of test sequences is described to save storage resources and reduce the number of candidate codewords. The external information calculation method without competing codewords and the improved decoding algorithm to improve the parallelism of the decoder are presented. The advantages of the improved decoding algorithm are analyzed and the decoding performance is theoretically analyzed. In addition, the simulation model of communication system is constructed by software, and the effects of different component codes, iterations, unreliable positions, quantization bits and channel types on TPC decoding performance are verified and analyzed. At the same time, the improved decoding algorithm is verified by simulation and performance analysis. Finally, the FPGA implementation of TPC codec is described in detail, and the main structure and improved scheme of the decoder are introduced in detail. The whole decoder uses a fully parallel input component code decoder, which can complete the input of the whole component code, compare and select the unreliable position, arrange the measurement value of the candidate codeword and calculate the external information. The parallelism of decoding is greatly increased, the delay of decoding is reduced, and the throughput of the system is improved effectively. In this paper, the XC7K355T chip of Kintex-7 series produced by Xilinx Company is used to complete the whole design. The whole design takes up 39% of the logic resource and 35% of the storage resource of the chip, and completes a comprehensive decoder. The integrated decoder accomplishes the decoding of the code 1024676 / 204881824) and the code 40966 / 32499). For the 1024676) code, the throughput of the decoder can be up to 274.80 Mbps. For the code 4096 / 3249, the throughput of the decoder can reach 571.34Mbps.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN911.22;TN791

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