折面相控阵雷达数字波束形成设计及实现

发布时间：2018-05-17 20:19

本文选题：相控阵 + 数字波束形成　；参考：《西安电子科技大学》2014年硕士论文

【摘要】：相控阵雷达以其波束灵活性等优点突破了常规雷达的许多限制,使得单部雷达能够同时完成跟踪、搜索等多个战术任务,从而形成了多功能相控阵雷达系统。由于雷达所安放的载体平台的需要,共形形式的相控阵应运而生,不仅解决了相控阵天线的安放问题,同时提高了雷达与载体平台的隐身性能。但天线形状的改变使得相控阵列的波束形成性能不同于常规规则几何布局的相控阵列。本文基于舰载火控相控阵雷达背景,主要针对某种分离折面相控阵进行了数字波束形成算法的仿真分析。然后通过分析算法需求,进行了基于该阵面的数字波束形成算法的工程开发与实现。本文首先从基本的平面相控阵开始,讨论了数字波束形成算法的处理过程及仿真结果。讨论了在大尺寸相控阵面下所采用的两级加权形式的数字波束形成方法,以及在该形式下的和波束及差波束形成方法。通过逐步对平面阵列进行变换依次形成折面阵和分离形式的折面阵,并对每种形式的阵面进行了和波束及差波束的仿真分析,给出了由于阵面的形状变化所产生的不同影响。其次本文依据数字波束形成算法的计算特点进行了硬件平台的设计。通过对光纤接收能力、信号处理能力以及数据吞吐能力三个方面的分析,提出了硬件平台的设计要求。依据设计要求进行了合理的处理芯片选择,形成了以FPGA和DSP为主的硬件处理平台。通过对电源、时钟等主要部分的设计,最终设计出能够满足本文所讨论的数字波束形成需要的硬件平台系统。最后本文在所设计的硬件平台上进行了数字波束形成算法的开发及实现。本文首先以自顶向下的方式对FPGA程序进行了系统设计,给出了一种合理的、可扩展的系统模块连接方式。然后针对系统中的数字波束形成计算、FPGA间通信、链路口通信等主要模块进行了详细设计。其数字波束形成计算部分基于FPGA内部结构,构建了一种高度并行的计算结构,保证了计算的实时性。针对FPGA间高速通信不稳定的问题,在对时序进行了仔细分析后,采用了一种延时补偿方式,保证了通信端口的传输速率和传输性能。基于FPGA设计的特点,本文通过对内部模块的分析,优化了各模块的内部布局,使得实现结果更加稳定。对该平台内的DSP,本文设计了一种固化启动方式,克服了传统代码包含方法的缺点,并具有更好的普适性和易操作性;同时设计了合理的DSP程序系统流程,简化了子功能程序设计和后续扩展。最后以某种波形为测试数据,对该系统中的每个环节及最后结果进行了软件仿真和在线测试,验证了设计的可行性和正确性。
[Abstract]:Phased array radar breaks through many limitations of conventional radar because of its advantages such as beam flexibility, which enables single radar to complete multiple tactical tasks such as tracking and searching simultaneously, thus forming a multi-function phased array radar system. Due to the need of carrier platform, conformal phased array emerges as the times require, which not only solves the problem of phased array antenna placement, but also improves the stealth performance of radar and carrier platform. However, the beamforming performance of phased array is different from that of conventional regular geometric layout due to the change of antenna shape. In this paper, based on the background of shipborne fire phased array radar, the digital beamforming algorithm is simulated and analyzed for a separated folded phased array. Then, by analyzing the requirements of the algorithm, the digital beamforming algorithm based on the array surface is developed and implemented. This paper begins with the basic planar phased array and discusses the processing process and simulation results of the digital beamforming algorithm. A two-stage weighted digital beamforming method for large size phased array is discussed, and the sum beam and differential beamforming method in this form are also discussed. By transforming the plane array in turn to form a folded plane array in turn and a folded plane array in separate form, and the simulation analysis of the sum beam and the difference beam of each kind of plane, the different effects caused by the shape change of the array surface are given. Secondly, the hardware platform is designed according to the computing characteristics of digital beamforming algorithm. The design requirements of the hardware platform are put forward through the analysis of the optical fiber receiving ability, the signal processing ability and the data throughput capability. According to the design requirements, the reasonable processing chip selection is carried out, and the hardware processing platform based on FPGA and DSP is formed. Through the design of power supply, clock and other main parts, the hardware platform system which can meet the need of digital beamforming discussed in this paper is designed. Finally, the digital beamforming algorithm is developed and implemented on the hardware platform. In this paper, the FPGA program is designed in a top-down way, and a reasonable and extensible system module connection mode is given. Then the main modules such as communication between FPGA and link intersection are designed in detail. The digital beamforming computing part is based on the internal structure of FPGA, and a highly parallel computing structure is constructed, which ensures the real-time computing. Aiming at the instability of high-speed communication between FPGA, a delay compensation method is adopted after careful analysis of the timing, which ensures the transmission rate and performance of the communication port. Based on the characteristics of FPGA design, this paper optimizes the internal layout of each module by analyzing the internal module, which makes the result more stable. For the DSP in this platform, this paper designs a solidification startup method, which overcomes the shortcomings of the traditional code inclusion method, and has better universality and ease of operation, and also designs a reasonable DSP program system flow. Simplifies subfunction programming and subsequent extensions. Finally, taking a certain waveform as test data, the software simulation and online test of each link and the final results of the system are carried out, and the feasibility and correctness of the design are verified.
【学位授予单位】：西安电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN958.92

【引证文献】