基于时间交替的数据采集系统设计与实现

发布时间：2018-05-19 06:37

  本文选题：功耗攻击 + 时间交替　； 参考：《国防科学技术大学》2014年硕士论文

【摘要】：功耗攻击对密码芯片的安全很具威胁,它通过采集密码芯片的瞬态功耗信息从而推算其密钥,是一种有效的攻击手段。为了更好的进行功耗攻击,针对密码芯片工作频率高,加密部件占总芯片比例较小等特点,本文设计了一套高速高精度的瞬态功耗采样系统。时间交替采样是在保证精度的前提下提高采集速度的一种有效方法,它采用多片相对低速的高精度ADC按照时间交替的方式并行采样。本文针对时间交替数据采集系统通道失配误差的校正问题,提出了一种频域时域相结合的校正方法。该方法采用板载信号源,校准源时钟和采集时钟同源同步,基于FARROW结构的滤波器补偿误差等多种手段,提高了通道失配误差校正的准确性。实测结果表明:ADC在5GSPS采样率的情况下,校准后SNR和SINAD提升达到30%,SFDR提升达到60%,说明该方法对误差有很好的校正效果。时钟抖动对时间交替采样系统的精度有较大影响。本文采用时钟源改进、分频器和带通滤波器的使用、时钟链路元件数量缩减等一系列抑制抖动的方法,设计实现了一个超低抖动的时钟产生电路。实测结果表明:该电路产生2.5GHz时钟时,噪声抖动仅有89.0fs RMS,满足了时间交替数据采集系统的需求。以前述技术为基础,本项目组设计并实现了一套基于时间交替的数据采集系统,它由模拟信号输入、时钟产生分配、电源管理、模数转换、数据接收缓存和数据处理上报六个子模块组成,对整个系统性能的实测结果表明:该系统在达到5GSPS采样率的同时,采样精度达到8位以上。
[Abstract]:Power attack is a threat to the security of cipher chip. It is an effective attack method by collecting the transient power information of cipher chip and calculating its key. In order to attack the power consumption better, a high speed and high precision transient power sampling system is designed to solve the problem of high frequency of cipher chip and small proportion of encryption components. The time alternating sampling is an effective method to improve the acquisition speed under the premise of ensuring the precision. It adopts the multi-chip relatively low speed high precision ADC to sample in parallel according to the time alternating mode. In order to correct the channel mismatch error of time alternating data acquisition system, a frequency domain combined correction method is proposed in this paper. In this method, the accuracy of channel mismatch correction is improved by means of on-board signal source, calibrating source clock and collecting clock homologous synchronization, filter compensation error based on FARROW structure and so on. The measured results show that under the 5GSPS sampling rate, the SNR and SINAD elevations after calibration can reach 30% and 60% respectively, which shows that the proposed method has a good correction effect on the errors. Clock jitter has great influence on the precision of time alternating sampling system. In this paper an ultra-low jitter clock generation circuit is designed and implemented by a series of methods such as clock source improvement the use of frequency divider and bandpass filter and the reduction of the number of clock link elements. The experimental results show that when the 2.5GHz clock is generated, the noise jitter is only 89.0fs RMS, which meets the requirement of the time alternating data acquisition system. Based on the above technology, the project team designs and implements a data acquisition system based on time alternation, which is composed of analog signal input, clock generation and distribution, power management, A / D conversion, etc. Six sub-modules are composed of data receiving buffer and data processing and reporting. The measured results of the whole system performance show that the system achieves the 5GSPS sampling rate and the sampling accuracy reaches more than 8 bits at the same time.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TP274.2;TN918.4
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本文编号：1909084