Turbo乘积码译码技术的研究与实现

发布时间：2018-05-25 22:53

本文选题：信道编码 + Turbo乘积码　；参考：《东北大学》2014年硕士论文

【摘要】：信道编码技术是数字通信系统中的关键技术之一,它已成为现代通信学科中最重要的分支之一。人们一直致力于寻找一种性能接近香农极限,并且译码复杂度较低的编码方案。1994年,Pyndiah等人提出了Turbo乘积码(TPC),它继承了Turbo码在性能上接近香农极限的优点,而且译码复杂度比Turbo码低,近年来已逐渐成为信道编码领域的研究热点。本文首先介绍了Turbo乘积码的构造以及编译码原理,然后重点研究了Turbo乘积码的硬判决和软判决译码算法,对基于Chase算法的软判决迭代译码算法进行了改进。在Matlab2008环境下对改进前后的译码算法进行了仿真验证,并对仿真结果进行了分析和比较,得出各种译码算法的优缺点。仿真结果表明,改进后的译码算法比原始译码算法在性能上有所提高。同时对各种影响Turbo乘积码性能的因素也进行了仿真,并对仿真结果做了对比和分析。在Matlab仿真的基础上,提出了Turbo乘积码的FPGA设计方案,并详尽阐述了用FPGA实现TPC码译码的整体设计方案、实现流程和各个模块的具体实现方法。子码采用了加一位奇偶校验位的(54,47)截短BCH码。在FPGA设计时,采用自顶向下的设计思想,将系统划分为若干子模块,使系统的设计更加灵活。在ISE9.2环境下,以Xilinx公司的spartan-3系列中的xc3s4000-4FG676芯片为目标芯片,采用Verilog硬件描述语言完成了TPC译码器的设计、综合,并在Modelsim10.0C环境下进行了时序仿真。仿真结果表明,用FPGA设计的译码算法在性能上与Matlab仿真结果一致。在文章的结尾部分,总结了研究成果。指出了有待改进的地方,并提出了下一步工作计划。
[Abstract]:Channel coding is one of the key technologies in digital communication systems. It has become one of the most important branches of modern communication science. People have been working hard to find a coding scheme with performance close to Shannon limit and low decoding complexity. In 1994, Pyndiah et al proposed Turbo product code, which inherits the advantages of Turbo code in performance approaching Shannon limit. Moreover, the decoding complexity is lower than that of Turbo code, so it has gradually become a hotspot in the field of channel coding in recent years. This paper first introduces the construction of Turbo product codes and the encoding and decoding principles, then focuses on the hard decision and soft decision decoding algorithms of Turbo product codes, and improves the soft decision iterative decoding algorithm based on Chase algorithm. The improved decoding algorithms are verified by simulation in Matlab2008 environment, and the simulation results are analyzed and compared, and the advantages and disadvantages of various decoding algorithms are obtained. Simulation results show that the performance of the improved decoding algorithm is better than that of the original decoding algorithm. At the same time, various factors affecting the performance of Turbo product codes are simulated, and the simulation results are compared and analyzed. On the basis of Matlab simulation, the FPGA design scheme of Turbo product code is put forward, and the whole design scheme of decoding TPC code with FPGA is described in detail, the realization flow and the concrete realization method of each module are described in detail. The subcode is a truncated BCH code with a parity check bit. In the design of FPGA, the top-down design idea is used to divide the system into several sub-modules, which makes the design of the system more flexible. In ISE9.2 environment, the xc3s4000-4FG676 chip of spartan-3 series of Xilinx Company is taken as the target chip, and the design of TPC decoder is completed by using Verilog hardware description language, and the time sequence simulation is carried out under the environment of Modelsim10.0C. Simulation results show that the performance of the decoding algorithm designed by FPGA is consistent with that of Matlab simulation. At the end of the article, the research results are summarized. The paper points out the areas to be improved and puts forward the next work plan.
【学位授予单位】：东北大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN911.22

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