高吞吐率Turbo译码器设计与实现

发布时间：2018-05-31 10:35

本文选题：Turbo码 + 并行译码　；参考：《西南交通大学》2014年硕士论文

【摘要】：Turbo码在数字通信中的重要性众所周知,其几乎接近香农理论极限的译码性能,使得它在各类无线通信系统中被广泛应用,深空通信、卫星通信以及B3G移动通信系统等都将Turbo码作为信道编译码方案。为满足未来通信系统上百兆信息传输速率的需求,设计出高速的Turbo译码器尤为关键。本文以设计高吞吐率的译码器为目标,着重研究了Turbo码译码算法及基于FPGA的硬件实现技术。本文首先介绍了Turbo码编译码原理,然后分析了目前常用的几种译码算法,在此基础上权衡译码性能以及硬件实现复杂度两方面,选取了复杂度低并且性能有所改善的Enhanced-Max-Log-MAP译码算法作为本文Turbo译码器的硬件实现算法。在基于FPGA的硬件实现中,为得到较高的译码吞吐率,本文从算法结构以及工作时钟频率两方面考虑,在算法结构方面,采用分块并行译码、滑窗译码、迭代停止判决准则等高速译码方案降低译码时延,并搭建Turbo译码器软件仿真平台,对影响译码器性能的参数进行仿真,给出Turbo译码器的最佳实现方案。在时钟频率优化方面,通过采用“流水线结构”等技术,提高译码器工作时钟频率。基于上述方案,本文采用Verilog DHL代码进行Turbo译码算法设计,通过Matlab和Modelsim仿真工具搭建硬件仿真平台完成功能仿真验证,在基于Xilinx Virtex-6LX240T FPGA芯片的FT4000系统上完成译码器的系统验证,并对译码器的资源消耗和吞吐率性能进行分析,最终本文设计的译码器在码块长度6144bit,并行度8,6次迭代的情况下,译码吞吐率满足100Mbps的性能需求。
[Abstract]:The importance of Turbo code in digital communication is well known, and its decoding performance is close to the limit of Shannon's theory, which makes it widely used in all kinds of wireless communication systems, deep space communication. Satellite communication and B3G mobile communication system take Turbo code as channel coding and decoding scheme. In order to meet the demand of 100 megabit information transmission rate in future communication system, it is very important to design a high speed Turbo decoder. In order to design a decoder with high throughput, this paper focuses on the decoding algorithm of Turbo code and the hardware implementation technology based on FPGA. This paper first introduces the principle of Turbo coding and decoding, then analyzes several decoding algorithms which are commonly used at present. On this basis, the decoding performance and the complexity of hardware implementation are weighed. The Enhanced-Max-Log-MAP decoding algorithm with low complexity and improved performance is selected as the hardware implementation algorithm of the Turbo decoder in this paper. In the hardware implementation based on FPGA, in order to get high throughput, this paper considers the algorithm structure and the working clock frequency. In the aspect of algorithm structure, block parallel decoding and sliding window decoding are adopted. High speed decoding scheme such as iterative stop decision criterion is used to reduce decoding delay. The software simulation platform of Turbo decoder is built to simulate the parameters that affect the performance of the decoder. The optimal implementation scheme of Turbo decoder is given. In the aspect of clock frequency optimization, the clock frequency of decoder is improved by adopting pipeline structure and other techniques. Based on the above scheme, the Turbo decoding algorithm is designed with Verilog DHL code, the hardware simulation platform is built by Matlab and Modelsim simulation tools, and the system verification of the decoder is completed on the FT4000 system based on Xilinx Virtex-6LX240T FPGA chip. The resource consumption and throughput performance of the decoder are analyzed. Finally, the decoding throughput meets the performance requirements of 100Mbps under the condition of block length of 6144 bits and parallel degree of 86 iterations.
【学位授予单位】：西南交通大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN911.2

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