数字中频无线接收机的研究与设计

发布时间：2018-06-01 06:29

本文选题：数字中频接收机 + 射频前端模块　；参考：《河北工业大学》2015年硕士论文

【摘要】：本论文课题来源于中国电子科技集团公司第十三研究所“无线语音侦听系统”,该项目需要对载波频率为450MHz至460MHz、数据速率为200KBps、调制方式为二进制相移键控(BPSK)或差分二进制相移键控(DBPSK)的语音PCM编码信号进行接收、解调、解码和播放存储。在此项目背景下,本文研究设计了一套灵敏度高、抗噪声能力强、适用多种解调方式的无线接收机。本文从现有通信技术入手,以软件定义无线电(SDR)的思想和结构为基础,设计并实现了一套数字中频无线接收机,其中包括三部分:一是射频前端模块(RFAF),此模块包括天线、低噪声放大器(LNA)、带通滤波器(BPF)、频率源、下混频器和中频放大器等,其功能是处理射频模拟信号,对其进行接收、放大、滤波、混频,最终产生一个频率和幅度固定的中频信号;二是数字中频处理模块,此模块包括模数转换器(ADC)、数模转换器(DAC)和数字信号处理芯片(DSP或者FPGA),其功能是对中频信号进行采样,并利用数字信号处理技术完成解调解码等工作;三是接口和上位机处理模块,此模块提供了接收机与计算机的接口,在必要时进行数据的存储和分析处理,具体到本文,需要对解调解码出来的语音信号进行去噪声处理。本文在设计过程中,使用simulink进行了系统级仿真和可行性验证、使用ADS进行了射频模块的仿真和优化、使用Altium Designer进行了PCB板设计并进行了射频部分的硬件实验、使用modelsim和matlab进行了FPGA和解调解码算法仿真优化、最终使用SignalTap等工具进行了中频部分的硬件调试和实验。根据软件仿真和硬件调试结果,本文设计的数字中频无线接收机达到如下参数指标:射频部分接收灵敏度到达-100dB,1KHz带外相位噪声小于-60dBc,频道切换时间小于60us;数字中频模块输入信号信噪比(SNR)最低可达5dB、FPGA最高运行频率可达200MHz;通过改进的谱减法进行语音去噪,在实际应用中明显降低了接收者的听觉疲劳,提高了语音信号可懂度。
[Abstract]:This thesis comes from the 13th Research Institute of China Electronic Science and Technology Corporation, "Wireless Voice listening system". This project needs to receive, demodulate, decode and store speech PCM code signals with carrier frequencies ranging from 450MHz to 460MHz, data rate 200KBps, modulation mode by binary phase-shift keying (BPSK) or differential binary phase-shift keying (DBPSK). Under the background of this project, a set of wireless receiver with high sensitivity, strong anti-noise ability and suitable for various demodulation methods is designed. Based on the idea and structure of software defined radio SDR (SDR), a set of digital if wireless receiver is designed and implemented in this paper, which includes three parts: one is RF front-end module (RFAFN), which includes antenna, and the other is radio frequency front-end module (RF front-end module). Low noise amplifier (LNA), bandpass filter (BPF), frequency source, lower mixer and if amplifier, etc. Its function is to process RF analog signal, receive, amplify, filter, mix frequency, and finally produce a fixed frequency and amplitude if signal; The second is digital intermediate frequency processing module, which includes A / D converter (A / D converter), D / A converter (DAC) and digital signal processing chip (DSP) or FPGA. Its function is to sample if signal and complete demodulation and decoding by means of digital signal processing technology. The third is the interface and the upper computer processing module which provides the interface between the receiver and the computer. The data is stored and analyzed when necessary. In this paper it is necessary to remove the noise from the demodulated and decoded speech signal. In the design process, the system level simulation and feasibility verification are carried out with simulink, the RF module is simulated and optimized with ADS, the PCB board is designed with Altium Designer and the hardware experiment of RF part is carried out. Modelsim and matlab are used to simulate and optimize the FPGA and demodulation decoding algorithm. Finally, the hardware debugging and experiment of if part are carried out by using SignalTap and other tools. According to the results of software simulation and hardware debugging, The digital if wireless receiver designed in this paper achieves the following parameters: the sensitivity of the RF part reaches -100dBU 1kHz out-of-band phase noise is less than -60dBc, the channel switching time is less than 60us.The SNR of the input signal of the digital intermediate frequency module is the lowest. The highest operating frequency of FPGA is up to 200MHz, and the speech noise is removed by improved spectral subtraction. In practical application, the hearing fatigue of the receiver is obviously reduced, and the intelligibility of speech signal is improved.
【学位授予单位】：河北工业大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN851

【参考文献】