基于FPGA的收发信机中频及基带设计

发布时间：2018-06-01 16:34

本文选题：无线通信 + FPGA　；参考：《电子科技大学》2014年硕士论文

【摘要】：本文结合通信原理基础知识介绍了无线收发信机中频及基带的各部分实现过程,所采用的方法具有典型性和实用性,而且不失创新性。本文采用一片Cyclone III系列的FPGA作为基带算法核心处理器,系统整体采用QPSK调制解调方式,在发射机端实现了串并转换、符号映射、基带成形滤波等核心算法;在接收机端实现了载波同步、符号同步以及帧同步等核心算法。本文通过对比各个方案的特点,结合模块化设计的特殊要求最后选择典型的超外差结构实现收发信机的硬件电路设计。本文选择ADI公司的正交变频器实现基带信号的调制与解调,并选择通信系统专用的TxDAC和RxADC实现了基带信号的数/模与模/数变换。此外本文介绍了本振时钟源(小数分频PLL)的驱动程序设计,使得中频及射频的本振频率可细调,调整步进为50KHz。发射机对输入串行数据首先进行加扰,然后按照QPSK调制方式进行了星座映射。发射机的脉冲成形滤波器为跟升余弦滚降滤波器,在本文中采用了基于FPGA的FIR滤波器的实现结构。接收机的重点是同步。本文通过对标准科斯塔斯环进行研究并结合硬件电路的实际情况最后采用了反馈补偿法载波同步。此外,本文在符号同步算法的实现上有所创新,提出了一种基于反馈环路形式的积分反馈式早迟门法。载波同步与符号同步在实现结构上相似,都采用反馈环路的形式。试验证明本文采用的载波同步与符号同步算法原理可行、性能良好。本文中的FPGA开发采用“自顶向下”的设计思路,将复杂的功能模块划分成功能单一的底层模块,再由Verilog HDL语言逐一描述。FPGA具有极强的实时性和并行处理能力,可以满足通信系统对处理器性能的需求。本文的最终成果实现了中频段140MHz的通信,同时,通过配合射频前端模块实现了2.45GHz射频段的无线通信。本文的基带部分具有1M symbol/s的符号率,并具备2M bps的数据传输速率。为了方便测试,本文设计了完善的对外交换数据的通信接口,该通信接口具备数据缓存功能,为将上层主机(PC、MCU)数据源注入收发机系统提供了途径,同时也增强了系统的实用性。
[Abstract]:In this paper, the realization process of if and baseband of wireless transceiver is introduced based on the basic knowledge of communication principle. The method adopted is typical, practical and innovative. In this paper, a Cyclone III series of FPGA is used as the core processor of baseband algorithm, and the whole system adopts QPSK modulation and demodulation mode. The core algorithms such as serial-parallel conversion, symbol mapping, baseband shaping filtering and so on are implemented in the transmitter. The core algorithms such as carrier synchronization, symbol synchronization and frame synchronization are implemented at the receiver end. By comparing the characteristics of each scheme and combining the special requirements of modular design, this paper chooses the typical superheterodyne structure to realize the hardware circuit design of transceiver. In this paper, the quadrature frequency converter of ADI Company is selected to realize the modulation and demodulation of baseband signal, and the TxDAC and RxADC, which are special for communication system, are selected to realize the digital / analog and A / D conversion of baseband signal. In addition, this paper introduces the driver design of the local oscillator clock source (fractional divider PLL), which makes the local frequency of if and RF can be fine-tuned and the step is adjusted to 50 KHz. The transmitter scrambled the input serial data and then mapped the constellation according to QPSK modulation. The pulse shaping filter of the transmitter is the following cosine roll down filter. The FIR filter based on FPGA is adopted in this paper. The focus of the receiver is synchronization. In this paper, the standard Kostas loop is studied and the feedback compensation method is used to synchronize the carriers. In addition, in this paper, the implementation of symbol synchronization algorithm is innovated, and an integral feedback early and late gate method based on feedback loop is proposed. Carrier synchronization and symbol synchronization are similar in structure, and both adopt feedback loop. The experimental results show that the carrier synchronization and symbol synchronization algorithms are feasible and have good performance. The development of FPGA in this paper adopts the idea of "top-down" design. The complex function module is divided into a single bottom module, and then described by Verilog HDL language one by one, it has strong real-time and parallel processing ability. It can meet the requirement of processor performance in communication system. The final achievement of this paper is to realize the communication of 140MHz in the middle frequency band, and to realize the wireless communication of the radio frequency segment of 2.45GHz by cooperating with the RF front-end module. The baseband of this paper has a symbol rate of 1m symbol/s and a data transmission rate of 2m bps. In order to facilitate the test, this paper designs a perfect communication interface for data exchange. The communication interface has the function of data cache, which provides a way to inject the data source of PC / MCU into the transceiver system, and at the same time enhances the practicability of the system.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN791;TN859

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