锁相环测试方法与测试板开发

发布时间：2018-06-02 02:05

  本文选题：PLL测试 + 抖动因素　； 参考：《国防科学技术大学》2014年硕士论文

【摘要】：锁相环(PLL)作为时钟芯片广泛应用于无线通信、消费电子等现代IC产品中,其功能包括相位同步和时钟倍频等。衡量PLL性能优劣的关键指标之一为抖动(在频域表现为相位噪声)特性,在PLL芯片测试中,如何精确衡量PLL的时钟抖动特性已成为日渐重要的课题。针对PLL的抖动评估,在设计阶段的电路模拟远远不够,只有对流片后的成品芯片进行功能验证和可靠性测试,才能最终断言设计是否正确。本文将详细阐述PLL芯片的测试原理与抖动因素探究,具体工作如下:(1)阐述PLL的工作原理、噪声分析及电路级抖动模拟。(2)搭建PLL测试平台,分析抖动参数的物理意义,应用示波器、相噪仪、测试板、数据分析软件等设备对实体芯片进行各项指标测量,以验证PLL的性能。(3)重点分析引起PLL抖动的主要因素,阐述抖动的分类机制、抖动分解测试原理、探头效应等。通过对照实验、多次重复实验、控制变量法等测试方法,深入透彻地分析抖动来源及形成机理,并给出了降低外部抖动的测试方案,减小测试引入的误差。(4)为了获得高精度、高稳定度的测试板,以便更加准确地测试PLL的抖动指标,本文还对PLL测试板进行了优化设计,从电路设计、PCB设计及元器件选型等方面,详细叙述了测试板开发的流程。最后应用新设计的测试板进行重复实验,测试结果表明新测试板_V2.0在稳定度方面大幅提升,外部噪声明显减小,能更加准确地衡量PLL的抖动指标。本文从PLL芯片测试背景、测试系统固化、测试标准统一、测试方法规范等角度,全面论述了PLL芯片测试的系统方法,对时钟抖动的研究有极其重要的意义。
[Abstract]:As a clock chip, PLL is widely used in modern IC products such as wireless communication, consumer electronics and so on. Its functions include phase synchronization and clock frequency doubling. One of the key indexes to measure the performance of PLL is jitter (phase noise in frequency domain). In PLL chip testing, how to accurately measure the clock jitter of PLL has become an increasingly important issue. For the jitter evaluation of PLL, the circuit simulation in the design stage is far from enough. Only after the functional verification and reliability test of the finished chip behind the convection chip, can the design be finally determined whether the design is correct or not. In this paper, the testing principle and jitter factors of PLL chip are described in detail. The specific work is as follows: 1) expatiate the working principle of PLL, noise analysis and circuit level jitter analogue. Build the PLL test platform, analyze the physical meaning of jitter parameter. By using oscilloscope, phase noise meter, test board, data analysis software and other equipment to measure the index of entity chip, to verify the performance of PLL, to analyze the main factors that cause PLL jitter, and to expound the classification mechanism of jitter. Jitter decomposition test principle, probe effect and so on. In order to obtain high accuracy, the source and formation mechanism of jitter are thoroughly analyzed by means of control experiment, repeated experiment, control variable method and so on. The test scheme to reduce the external jitter is given, and the error introduced in the test is reduced. The test board with high stability is used to test the jitter index of PLL more accurately. This paper also optimizes the design of PLL test board, and describes the development process of the test board in detail from the aspects of circuit design, PCB design and components selection. The test results show that the stability of the new test board V2.0 is greatly improved, the external noise is obviously reduced, and the jitter index of PLL can be measured more accurately. From the point of view of PLL chip test background, test system solidification, uniform test standard and test method specification, this paper discusses the system method of PLL chip testing, which is of great significance to the research of clock jitter.
【学位授予单位】：国防科学技术大学
【学位级别】：硕士
【学位授予年份】：2014
【分类号】：TN911.8
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本文编号：1966817