基于FPGA的射频收发机实验系统的设计与实现

发布时间：2018-06-06 14:15

本文选题：FPGA + 无线通信　；参考：《电子科技大学》2015年硕士论文

【摘要】：随着通信技术的发展,无线通信相关实验教学受到越来越多的高校重视,对于无线通信实验课程来说,良好的实验系统必不可少。因此,构建一套完善的无线通信实验系统对培养学生创新能力、工程素养和提高对无线通信相关技术的理解具有重要意义。本实验系统是一套超外差结构射频收发机实验系统,使用软件定义无线电的技术,基带系统具有软件可编程、可重构特性,射频和中频电路也具有重新设定的能力,主要表现在工作频率可调;硬件结构兼顾了超外差结构和零中频结构,满足了通用性和兼容性的要求。硬件系统的设计难点在于数模混合电路的设计和信号完整性。本设计通过优化布局布线,隔离数字芯片和模拟芯片以增加数模隔离度,优化电源模块,降低电源纹波从而抑制了噪声的传播,提高了系统的信噪比。基带部分以ALTERA公司的CycloneIII芯片为核心进行基带信号的处理,辅以一块ARM芯片作为控制芯片。数模转换和模数转换采用通信系统专用的高速TxDAC和Rx ADC,基带信号的调制解调选用ADI公司的正交变频器,接收机基带部分使用一块AGC芯片进行接收信号的增益控制,本振信号源使用锁相环的方法实现,信号源的频率可调。系统自身可实现中频140MHz的通信,配合射频前端可实现2.4GHz-2.48GHz的无线射频通信。本实验系统可以进行不同频的双工通信,发射机和接收机的基带信号处理程序同时运行于一块FPGA,采用硬件编程语言Verilog实现这些算法。基带算法设计采用自顶向下的设计方法,将整个系统分成若干模块,模块下又分成若干子模块,这样设计系统层次分明、结构清晰。发射机基带信号处理包括视频信号采集、并串转换、幅度调制、伪随机编码、脉冲成形滤波等算法;接收机的基带信号处理包括载波同步、符号同步、伪随机解码、幅度解调和串并转换等算法。基带信号处理的核心算法有FIR滤波、载波同步、位同步等。使用高效的IP核实现了FIR滤波,大大提高了设计效率。载波同步和位同步都是用了反馈控制的方法来使同步更精确。
[Abstract]:With the development of communication technology, more and more colleges and universities attach importance to wireless communication experiment teaching, and a good experimental system is essential for wireless communication experiment course. Therefore, it is of great significance to construct a perfect wireless communication experimental system for cultivating students' innovation ability, engineering accomplishment and understanding of wireless communication related technology. This experiment system is an experimental system of radio transceiver with superheterodyne structure. The technology of defining radio by software is used. The baseband system has the characteristics of software programmable and reconfigurable, and the radio frequency and intermediate frequency circuits also have the ability to reconfigure. The main performance is that the working frequency is adjustable, and the hardware structure takes into account both the superheterodyne structure and the zero-intermediate frequency structure, which meet the requirements of universality and compatibility. The design difficulty of hardware system lies in the design of digital-analog hybrid circuit and signal integrity. Through optimizing layout and wiring, isolating digital chip and analog chip to increase the degree of digital-analog isolation, optimizing the power supply module, reducing the ripple of power supply, thus restraining the spread of noise and improving the signal-to-noise ratio of the system. The baseband part uses ALTERA CycloneIII chip as the core to process the baseband signal, and a ARM chip is used as the control chip. Digital-to-analog conversion and analog-to-digital conversion use high-speed TxDAC and RxADC. the modulation and demodulation of baseband signal is based on the quadrature frequency converter of ADI Company. The baseband part of the receiver uses a AGC chip to control the gain of the received signal. The method of phase-locked loop is used to realize the local oscillator signal source, and the frequency of the signal source can be adjusted. The system can realize if 140MHz communication and 2.4GHz-2.48GHz radio frequency communication with RF front end. The experimental system can be used for duplex communication with different frequencies. The baseband signal processing program of transmitter and receiver runs in a FPGA at the same time. These algorithms are implemented by hardware programming language Verilog. The design of baseband algorithm adopts top-down design method, the whole system is divided into several modules, and the module is divided into several sub-modules, so the design system is structured clearly and clearly. Transmitter baseband signal processing includes video signal acquisition, parallel string conversion, amplitude modulation, pseudorandom coding, pulse shaping filtering and so on, and receiver baseband signal processing includes carrier synchronization, symbol synchronization, pseudorandom decoding, etc. Amplitude demodulation and serial-parallel conversion algorithms. The core algorithms of baseband signal processing are FIR filtering, carrier synchronization, bit synchronization and so on. The efficient IP core is used to realize the FIR filter, which greatly improves the design efficiency. Both carrier and bit synchronization uses feedback control to make synchronization more accurate.
【学位授予单位】：电子科技大学
【学位级别】：硕士
【学位授予年份】：2015
【分类号】：TN859

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